
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 5: The Clock Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
5-38
3
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
2:1
sel_clk_mem
R/W
00
00: clk_mem = PLL2
01: clk_mem = PLL2
10: clk_mem = 27 MHz xtal_clk
11: clk_mem = GPIO[7]
0
en_clk_mem
R/W
1
1: enable clk_mem
Offset 0x04,7108
CLK_2DDE_CTL
31:7
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
6
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
5:3
sel_clk_2dde_src
R/W
111
000: clk_2dde_src = clk_144
001: clk_2dde_src = clk_123
010: clk_2dde_src = clk_108
011: clk_2dde_src = clk_96
100: clk_2dde_src = clk_86
101: clk_2dde_src = clk_78
110: clk_2dde_src = clk_72
111: clk_2dde_src = clk_66
2:1
sel_clk_2dde
R/W
00
00: clk_2dde = 27 MHz xtal_clk
01: clk_2dde = clk_2d2_src
10: clk_2dde = 27 MHz xtal_clk
11: clk_2dde = AI_SD[1]
0
en_clk_2dde
R/W
1
1: enable clk_2dde
Offset 0x04,710C
CLK_PCI_CTL
31:4
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
3
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
2:1
sel_clk_pci
R/W
01
00: clk_pci = 27 MHz xtal_clk
01: clk_pci = clk_33
10: clk_pci = xtal_clk/16 = 1.68 MHz
11: clk_pci = AI_SD[2]
0
en_clk_pci
R/W
1
1: enable clk_pci
Offset 0x04,7110
CLK_MBS_CTL
31:7
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Table 11: CLOCK MODULE REGISTERS …Continued
Bit
Symbol
Acces
s
Value
Description