
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 11: QVCP
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
11-41
4.8.1
Layer Underow
Any time the layer position has reached but the small 16-pixel FIFO at the end of
every layer pipe has run out of available pixels, underow occurs.
4.8.2
Underow Symptom
Only portion of a picture is displayed or occasional blinking of picture happens
Underow interrupt bit is set.
4.8.3
Underow Recovery
Should an underow occur, the layer would fetch and dump remaining data for the
current eld/frame. The next eld/frame would be fetched and displayed as normal.
4.8.4
Underow Trouble-shooting
Check if the DMA source width settings (0x10,Ex08) matches the initial layer
width (0x10,Ex34)
Check if the initial layer width (0x10,Ex34) matches the nal layer width
(0x10,ExB4) for the non-scaled layer.
Check if the nal layer width (0x10,ExB4) is within acceptable cropping range for
LINT or HSRU scaling.
Check whether the DMA start fetch (0x10,ExC8) is at line number too close to the
display position. Note that about 64 pixels is QVCP’s input-to-output latency. So,
depending on the system-memory latency, the DMA fetch should start as early as
possible, in order to make up for the request-to-data latency.
Check if the system memory arbiter is giving high priority to QVCP.
Check if QVCP demands exceed allocated memory bandwidth.
4.8.5
Underow Handling
The underow interrupt status would stay asserted until an interrupt-status-clear is
programmed.
4.9 Setting QVCP for External VSYNC
Set the following bits in MMIO register 0x10,E020 as follows:
bit 1 (master) = 1;
bit 2 (Trigger_pol) = 1; for posisitive edge trigger
bit 16 (SYNCCtl) = 0; VSYNC pin becomes an input
bit 24 (VSYNCPol) = 0;