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| 型號(hào)： | 935273916557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PBGA156 |
| 封裝： | 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156 |
| 文件頁(yè)數(shù)： | 56/178頁(yè) |
| 文件大?。?/td> | 988K |
| 代理商： | 935273916557 |
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2004 Jul 22
149
Philips Semiconductors
Product specication
Multistandard video decoder with adaptive
comb lter and component video input
SAA7118
Table 111 Task handling control; register set A [90H[2:0]] and B [C0H[2:0]]; note 1
Note
1. X = don’t care.
15.7.6
SUBADDRESSES 91H TO 93H
Table 112 X port formats and conguration; register set A [91H[7:3]] and B [C1H[7:3]]; note 1
Note
1. X = don’t care.
EVENT HANDLER CONTROL
CONTROL BITS D2 TO D0
RPTSK
STRC1
STRC0
Event handler triggers immediately after nishing a task
X
0
Event handler triggers with next V-sync
X
0
1
Event handler triggers with eld ID = 0
X
1
0
Event handler triggers with eld ID = 1
X
1
If active task is nished, handling is taken over by the next task
0
X
Active task is repeated once, before handling is taken over by the next task
1
X
SCALER INPUT FORMAT AND CONFIGURATION SOURCE
SELECTION
CONTROL BITS D7 TO D3
CONLV
HLDFV
SCSRC1 SCSRC0
SCRQE
Only if XRQT[83H[2]] = 1: scaler input source reacts on
SAA7118 request
XXXX
0
Scaler input source is a continuous data stream, which cannot
be interrupted (must be logic 1, if SAA7118 decoder part is
source of scaler or XRQT[83H[2]] = 0)
XXXX
1
Scaler input source is data from decoder, data type is
provided according to Table 15
XX
0
X
Scaler input source is Y-CB-CR data from X port
X
0
1
X
Scaler input source is raw digital CVBS from selected analog
channel, for backward compatibility only, further use is not
recommended
XX
1
0
X
Scaler input source is raw digital CVBS (or 16-bit Y + CB-CR,if
no 16-bit outputs are active) from X port
XX
1
X
SAV/EAV code bits D6 and D5 (F and V) may change
between SAV and EAV
X
0
XXX
SAV/EAV code bits D6 and D5 (F and V) are synchronized to
scalers output line start
X
1
XXX
SAV/EAV code bit D5 (V) and V gate on pin IGPV as
generated by the internal processing; see Fig.43
0
XXXX
SAV/EAV code bit D5 (V) and V gate are inverted
1
XXXX
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