
2004
Jul
22
98
Philips
Semiconductors
Product
speci
cation
Multistandard
video
decoder
with
adaptiv
e
comb
lter
and
component
video
input
SAA7118
2004
Jul
22
98
Philips
Semiconductors
Product
speci
cation
Multistandard
video
decoder
with
adaptiv
e
comb
lter
and
component
video
input
SAA7118
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I port signal definitions
84
IDG01
IDG00
IDG11
IDG10
IDV1
IDV0
IDH1
IDH0
I port signal polarities
85
ISWP1
ISWP0
ILLV
IG0P
IG1P
IRVP
IRHP
IDQP
I port FIFO flag control and
arbitration
86
VITX1
VITX0
IDG02
IDG12
FFL1
FFL0
FEL1
FEL0
I port I/O enable, output clock
and gated clock phase control
87
IPCK3
IPCK2
IPCK1
IPCK0
IPE1
IPE0
Power save/ADC port control
88
DOSL1
DOSL0
SWRST
DPROG
SLM3
SLM1
SLM0
Reserved
89 to 8E
Status information scaler part
8F
XTRI
ITRI
FFIL
FFOV
PRDON
ERROF
FIDSCI
FIDSCO
TASK A DEFINITION: REGISTERS 90H TO BFH
Basic settings and acquisition window denition
Task handling control
90
CONLH
OFIDC
FSKP2
FSKP1
FSKP0
RPTSK
STRC1
STRC0
X port formats and conguration
91
CONLV
HLDFV
SCSRC1
SCSRC0
SCRQE
FSC2
FSC1
FSC0
X port input reference signal
denition
92
XFDV
XFDH
XDV1
XDV0
XCODE
XDH
XDQ
XCKS
I port output formats and
conguration
93
ICODE
I8_16
FYSK
FOI1
FOI0
FSI2
FSI1
FSI0
Horizontal input window start
94
XO7
XO6
XO5
XO4
XO3
XO2
XO1
XO0
95
XO11
XO10
XO9
XO8
Horizontal input window length
96
XS7
XS6
XS5
XS4
XS3
XS2
XS1
XS0
97
XS11
XS10
XS9
XS8
Vertical input window start
98
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
99
YO11
YO10
YO9
YO8
Vertical input window length
9A
YS7
YS6
YS5
YS4
YS3
YS2
YS1
YS0
9B
YS11
YS10
YS9
YS8
Horizontal output window length
9C
XD7
XD6
XD5
XD4
XD3
XD2
XD1
XD0
9D
XD11
XD10
XD9
XD8
Vertical output window length
9E
YD7
YD6
YD5
YD4
YD3
YD2
YD1
YD0
9F
YD11
YD10
YD9
YD8
REGISTER FUNCTION
SUB
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0