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參數(shù)資料
| 型號： | 935273916557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PBGA156 |
| 封裝： | 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156 |
| 文件頁數(shù)： | 138/178頁 |
| 文件大?。?/td> | 988K |
| 代理商： | 935273916557 |
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2004 Jul 22
62
Philips Semiconductors
Product specication
Multistandard video decoder with adaptive
comb lter and component video input
SAA7118
8.6.1
SCALER OUTPUT FORMATTER
(SUBADDRESSES 93H AND C3H)
The output formatter organizes the packing into the output
FIFO. The following formats are available:
Y-CB-CR 4:2:2, Y-CB-CR 4:1:1, Y-CB-CR 4:2:0,
Y-CB-CR 4 : 1 : 0 and Y only (e.g. for raw samples). The
formatting is controlled by FSI[2:0] 93H[2:0], FOI[1:0]
93H[4:3] and FYSK[93H[5]].
The data formats are dened on Dwords, or multiples, and
are similar to the video formats as recommended for PCI
multimedia applications (compares to SAA7146A), but
planar formats are not supported.
FSI[2:0] defines the horizontal packing of the data,
FOI[1:0] defines how many Y only lines are expected,
before a Y/C line will be formatted. If FYSK is set to logic 0
preceding Y only lines will be skipped, and the output will
always start with a Y/C line.
Additionally the output formatter limits the amplitude range
of the video data (controlled by ILLV[85H[5]]); see
Table 18.
Table 16 Byte stream for different output formats
Table 17 Explanation to Table 16
Table 18 Limiting range on I port
OUTPUT FORMAT
BYTE SEQUENCE FOR 8-BIT OUTPUT MODES
Y-CB-CR 4:2:2
CB0Y0
CR0Y1
CB2Y2
CR2Y3
CB4Y4
CR4Y5
CB6Y6
Y-CB-CR 4:1:1
CB0Y0
CR0Y1
CB4Y2
CR4
Y3Y4
Y5Y6
Y7
CB8Y8
Y only
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
NAME
EXPLANATION
CBnCB (B Y) colour difference component, pixel number n = 0, 2, 4 to 718
Yn
Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719
CRnCR (R Y) colour difference component, pixel number n = 0, 2, 4 to 718
LIMIT STEP
ILLV[85H[5]]
VALID RANGE
SUPPRESSED CODES (HEXADECIMAL VALUE)
DECIMAL VALUE
HEXADECIMAL VALUE
LOWER RANGE
UPPER RANGE
0
1 to 254
01 to FE
00
FF
1
8 to 247
08 to F7
00 to 07
F8 to FF
8.6.2
VIDEO FIFO (SUBADDRESS 86H)
The video FIFO at the scaler output contains 32 Dwords.
That corresponds to 64 pixels in 16-bit Y-CB-CR 4:2:2
format. But as the entire scaler can act as a pipeline buffer,
the actual available buffer capacity for the image port is
much higher, and can exceed beyond a video line.
The image port, and the video FIFO, can operate with the
video source clock (synchronous mode) or with an
externally provided clock (asynchronous and burst mode),
as appropriate for the VGA controller or attached frame
buffer.
The video FIFO provides 4 internal flags, reporting to what
extent the FIFO is actually filled.
These are:
The FIFO Almost Empty (FAE) flag
The FIFO Combined Flag (FCF) or FIFO filled, which is
set at almost full level and reset, with hysteresis, only
after the level crosses below the almost empty mark
The FIFO Almost Full (FAF) flag
The FIFO Overflow (FOVL) flag.
The trigger levels for FAE and FAF are programmable by
FFL[1:0] 86H[3:2] (16, 24, 28, full) and FEL[1:0] 86H[1:0]
(16, 8, 4, empty).
The state of this flag can be seen on the pins IGP0 or
IGP1. The pin mapping is defined by subaddresses
84H and 85H; see Section 9.6.
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