參數(shù)資料
型號： 935273916557
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號轉換
英文描述： COLOR SIGNAL DECODER, PBGA156
封裝： 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156
文件頁數(shù)： 33/178頁
文件大?。?/td> 988K
代理商： 935273916557
2004 Jul 22
128
Philips Semiconductors
Product specication
Multistandard video decoder with adaptive
comb lter and component video input
SAA7118
15.2.20 SUBADDRESS 13H
Table 59 RT/X port output control; 13H[7:0]
BIT
DESCRIPTION
SYMBOL
VALUE
FUNCTION
D7
RTCO output enable
RTCE
0
3-state
1
enabled
D6
X port XRH output
selection
XRHS
0
1
HS:
programmable width in LLC8 steps via HSB[7:0] 06H[7:0]
and HSS[7:0] 07H[7:0]
fine position adjustment in LLC2 steps via HDEL[1:0]
11H[5:4] (see Fig.30)
D[5:4] X port XRV output
selection
XRVS[1:0]
00
V123 (see Figs 28 and 29)
01
ITU 656 related eld ID (see Figs 28 and 29)
10
inverted V123
11
inverted ITU 656 related eld ID
D3
horizontal lock indicator
selection
HLSEL
0
copy of inverted HLCK status bit (default)
1
fast horizontal lock indicator (for special applications only)
D[2:0] XPD7 to XPD0 (port
output format selection);
see Section 9.5
OFTS[2:0]
000
ITU 656
001
ITU 656 like format with modied eld blanking according to
VGATE position (programmable via VSTA[8:0] 17H[0]
15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]])
010
Y-CB-CR 4 : 2 : 2 8-bit format (no SAV/EAV codes inserted)
011
reserved
100
multiplexed AD2/AD1 or AD4/AD3 bypass (bits D8 to D1)
dependent on mode settings (see Section 15.2.3); if two
ADCs are selected AD2/AD4 is output at CREF = 1 and
AD1/AD3 is output at CREF = 0
101
multiplexed AD2/AD1 or AD4/AD3 bypass (bits D7 to D0)
dependent on mode settings (see Section 15.2.3); if two
ADCs are selected AD2/AD4 is output at CREF = 1 and
AD1/AD3 is output at CREF = 0
110
reserved
111
multiplexed ADC MSB/LSB bypass dependent on mode
settings; only one ADC should be selected at a time;
ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0
are outputs at CREF = 0
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