參數(shù)資料
型號： 935273916557
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PBGA156
封裝： 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156
文件頁數(shù)： 136/178頁
文件大小： 988K
代理商： 935273916557
2004 Jul 22
60
Philips Semiconductors
Product specication
Multistandard video decoder with adaptive
comb lter and component video input
SAA7118
Table 14 Vertical phase offset usage; assignment of the phase offsets
Notes
1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper
output lines.
2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output
lines.
3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output
lines.
DETECTED INPUT
FIELD ID
TASK STATUS BIT
VERTICAL PHASE
OFFSET
CASE
EQUATION TO BE USED
0 = upper lines
0
YPY0[7:0] and
YPC0[7:0]
case 1(1) UP-UP (PHO)
case 2(2) UP-UP
case 3(3) UP-LO
0 = upper lines
1
YPY1[7:0] and
YPC1[7:0]
case 1
UP-UP (PHO)
case 2
UP-LO
case 3
UP-UP
1 = lower lines
0
YPY2[7:0] and
YPC2[7:0]
case 1
LO-LO
case 2
LO-UP
case 3
LO-LO
1 = lower lines
1
YPY3[7:0] and
YPC3[7:0]
case 1
LO-LO
case 2
LO-LO
case 3
LO-UP
PHO
YSCY[15:0]
64
-------------------------------
16
–
+
PHO
YSCY[15:0]
64
-------------------------------
16
–
+
8.5
VBI data decoder and capture
(subaddresses 40H to 7FH)
The SAA7118 contains a versatile VBI data decoder.
The implementation and programming model is in
accordance with the VBI data slicer built into the
multimedia video data acquisition circuit SAA5284.
The circuitry recovers the actual clock phase during the
clock run-in period, slices the data bits with the selected
data rate, and groups them into bytes. The result is
buffered into a dedicated VBI data FIFO with a capacity of
2
× 56 bytes (2 × 14 Dwords). The clock frequency, signal
source, field frequency and accepted error count must be
defined in subaddress 40H.
The supported VBI data standards are shown in Table 15.
For lines 2 to 24 of a field, per VBI line, 1 of 16 standards
can be selected (LCR24_[7:0] to LCR2_[7:0] in 57H[7:0] to
41H[7:0]: 23
× 2 × 4 bit programming bits).
The definition for line 24 is valid for the rest of the
corresponding field, normally no text data (video data)
should be selected there (LCR24_[7:0] = FFH) to stop the
activity of the VBI data slicer during active video.
To adjust the slicers processing to the input signal source,
there are offsets in the horizontal and vertical direction
available: parameters HOFF[10:0] 5BH[2:0] 59H[7:0],
VOFF[8:0] 5BH[4] 5AH[7:0] and FOFF[5BH[7]].
Contrary to the scalers counting, the slicers offsets define
the position of the H and V trigger events related to the
processed video field. The trigger events are the falling
edge of HREF and the falling edge of V123 from the
decoder processing part.
The relationship of these programming values to the input
signal and the recommended values are given in
Tables 5 to 8.
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