參數(shù)資料
型號(hào)： 935270056512
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68
封裝： PLASTIC, MS-018, SOT-188-2, LCC-68
文件頁(yè)數(shù)： 6/52頁(yè)
文件大?。?/td> 680K
代理商： 935270056512
Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Product data
Rev. 02 — 14 March 2003
14 of 49
9397 750 11192
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.5 Interrupts
The SC16C754 has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The interrupt enable register (IER) enables each of the six types
of interrupts and the INT signal in response to an interrupt generation. The IER can
also disable the interrupt system by clearing bits 0-3, 5-7. When an interrupt is
generated, the IIR indicates that an interrupt is pending and provides the type of
interrupt through IIR[5;0]. Table 6 summarizes the interrupt control functions.
It is important to note that for the framing error, parity error, and break conditions,
LSR[7] generates the interrupt. LSR[7] is set when there is an error anywhere in the
RX FIFO, and is cleared only when there are no more errors remaining in the FIFO.
LSR[4:2] always represent the error status for the received character at the top of the
RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the
new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all
zeros.
For the Xoff interrupt, if an Xoff ow character detection caused the interrupt, the
interrupt is cleared by an Xon ow character detection. If a special character
detection caused the interrupt, the interrupt is cleared by a read of the LSR.
Table 6:
Interrupt control functions
IIR[5:0]
Priority
level
Interrupt type
Interrupt source
Interrupt reset method
000001
None
none
000110
1
receiver line status
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
FE, PE, BI: all erroneous
characters are read from the
RX FIFO.
OE: read LSR
001100
2
RX time-out
stale data in RX FIFO
read RHR
000100
2
RHR interrupt
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level
(FIFO enable)
read RHR
000010
3
THR interrupt
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger level
(FIFO enable)
read IIR or a write to the THR
000000
4
modem status
MSR[3:0] = 0
read MSR
010000
5
Xoff interrupt
receive Xoff character(s)/special
character
receive Xon character(s)/Read of
IIR
100000
6
CTS, RTS
RTS pin or CTS pin change state from
active (LOW) to inactive (HIGH)
read IIR
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