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| 型號： | 935270056512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, MS-018, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大小： | 680K |
| 代理商： | 935270056512 |
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Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Product data
Rev. 02 — 14 March 2003
29 of 49
9397 750 11192
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.10 Enhanced feature register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 19
shows the enhanced feature register bit settings.
Table 18:
Interrupt priority list
Priority
level
IIR[5]
IIR[4]
IIR[3]
IIR[2]
IIR[1]
IIR[0]
Source of the interrupt
1
0
00110
Receiver Line Status error
2
0
01100
Receiver time-out interrupt
2
0
00100
RHR interrupt
3
0
00010
THR interrupt
4
0
00000
Modem interrupt
5
0
10000
Received Xoff signal/
special character
6
1
00000
CTS, RTS change of state
from active (LOW) to
inactive (HIGH)
Table 19:
Enhanced Feature Register bits description
Bit
Symbol
Description
7
EFR[7]
CTS ow control enable.
Logic 0 = CTS ow control is disabled (normal default condition).
Logic 1 = CTS ow control is enabled. Transmission will stop when a
HIGH signal is detected on the CTS pin.
6
EFR[6]
RTS ow control enable.
Logic 0 = RTS ow control is disabled (normal default condition).
Logic 1 = RTS ow control is enabled. The RTS pin goes HIGH when
the receiver FIFO HALT trigger level TCR[3:0] is reached, and goes
LOW when the receiver FIFO RESUME transmission trigger level
TCR[7:4] is reached.
5
EFR[5]
Special character detect.
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. Received data is
compared with Xoff-2 data. If a match occurs, the received data is
transferred to FIFO and IIR[4] is set to a logical 1 to indicate a special
character has been detected.
4
EFR[4]
Enhanced functions enable bit.
Logic 0 = Disables enhanced functions and writing to IER[7:4],
FCR[5:4], MCR[7:5].
Logic 1 = Enables the enhanced function IER[7:4], FCR[5:4], and
MCR[7:5] can be modied, i.e., this bit is therefore a write enable.
3-0
EFR[3:0]
Combinations of software ow control can be selected by programming
these bits. See Table 3 “Software ow control options (EFR[0:3])” on
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