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| 型號： | 935270056512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, MS-018, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 14/52頁 |
| 文件大?。?/td> | 680K |
| 代理商： | 935270056512 |
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Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Product data
Rev. 02 — 14 March 2003
21 of 49
9397 750 11192
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Table 10 lists and describes the SC16C754 internal registers.
[1]
These registers are accessible only when LCR[7] = 0.
[2]
The shaded bits in the above table can only be modied if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.
[3]
The Special Register set is accessible only when LCR[7] is set to a logic 1.
[4]
Enhanced Feature Register; Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BFHex’.
Table 10:
SC16C754 internal registers
A2 A1 A0 Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/
Write
General Register Set[1]
0
RHR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
0
THR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W
001IER
0/CTS
interrupt
enable[2]
0/RTS
interrupt
enable[2]
0/Xoff[2]
0/X sleep
mode[2]
modem
status
interrupt
receive
line status
interrupt
THR
empty
interrupt
Rx data
available
interrupt
R/W
0
1
0
FCR
RX
trigger
level
(MSB)
RX trigger
level (LSB)
0/TX
trigger
level
(MSB)[2]
0/TX
trigger
level
(LSB)[2]
DMA
mode
select
TX FIFO
reset
RX FIFO
reset
FIFO
enable
W
0
1
0
IIR
FCR[0]
0/CTS,
RTS
0/Xoff
interrupt
priority
bit 2
interrupt
priority
bit 1
interrupt
priority
bit 0
interrupt
status
R
0
1
LCR
DLAB
break
control bit
set parity
parity type
select
parity
enable
number of
stop bits
word
length
bit 1
word
length
bit 0
R/W
100MCR
1
× or
1
×/4
clock
TCR and
TLR
enable
0/Xon
Any
0/enable
loop-back
IRQ
enable
OP
FIFO
ready
enable
RTS
DTR
R/W
1
0
1
LSR
0/error in
RX FIFO
THR and
TSR empty
THR
empty
break
interrupt
framing
error
parity error overrun
error
data in
receiver
R
1
0
MSR
CD
RI
DSR
CTS
CD
RI
DSR
CTS
R
1
SPR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
TCR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
TLR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
FIFO
Rdy
0
RX FIFO
B status
RX FIFO
A status
0
TX FIFO
B status
TX FIFO
A status
R
Special Register Set[3]
0
DLL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0
1
DLH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
Enhanced Register Set[4]
0
1
0
EFR
Auto CTS Auto RTS
Special
character
detect
Enable
enhanced
functions
software
ow
control
bit 3
software
ow
control
bit 2
software
ow
control
bit 1
software
ow
control
bit 0
R/W
1
0
Xon1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
1
Xon2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
Xoff1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
Xoff2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
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