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| 型號： | 935270056512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, MS-018, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 25/52頁 |
| 文件大小： | 680K |
| 代理商： | 935270056512 |
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Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Product data
Rev. 02 — 14 March 2003
31 of 49
9397 750 11192
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.14 FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs
of both channels.
The FIFO Rdy register is a read-only register that can be accessed when any of the
two UARTs is selected CSA - CSD = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and
loop-back is disabled. The address is 111.
Table 22:
FIFO Ready Register bits description
Bit
Symbol
Description
7-4
FIFO Rdy[7:4]
0 = There are less than a RX trigger level number of characters
in the RX FIFO.
1 = The RX FIFO has more than a RX trigger level number of
characters available for reading or a time-out condition has
occurred.
3-0
FIFO Rdy[3:0]
0 = There are less than a TX trigger level number of spaces
available in the TX FIFO.
1 = There are at least a TX trigger level number of spaces
available in the TX FIFO.
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