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參數(shù)資料
| 型號： | 935270056512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, MS-018, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 46/52頁 |
| 文件大?。?/td> | 680K |
| 代理商： | 935270056512 |
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Philips Semiconductors - PIP - SC16C754; Quad UART with 64-byte FIFO
Product Information
SC16C754; Quad
UART with 64-byte
FIFO
Information as of 2003-04-22
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Parametrics
topGeneral description
The SC16C754 is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs,
automatic hardware/software flow control, and data rates up to 5 Mbits/s (3.3 V and 5 V). The SC16C754
offers enhanced features. It has a transmission control register (TCR) that stores receiver FIFO threshold
levels to start/stop transmission during hardware and software flow control. With the FIFO RDY register,
the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers
provide the user with error indications, operational status, and modem interface control. System interrupts
may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters
on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive
FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates
its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd,
or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow,
and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface
for modem control operations, and has software flow control and hardware flow control capabilities.
The SC16C754 is available in plastic LQFP80 and PLCC68 packages.
topFeatures
q
Pin compatible with SC16C654IA68 and SC16C554IA68 with additional enhancements
q
Up to 5 Mbits/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is 3 Mbits/s)
q
64-byte transmit FIFO
q
64-byte receive FIFO with error flags
q
Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt
generation
q
Software/hardware flow control
r
Programmable Xon/Xoff characters
r
Programmable auto-RTS and auto-CTS
q
Optional data flow resume by Xon any character
q
DMA signalling capability for both received and transmitted data
q
Supports 5 V, 3.3 V and 2.5 V operation
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