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參數(shù)資料
| 型號： | 908E621_07 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror |
| 中文描述： | 綜合四半橋和三高的嵌入式微控制器和LIN高端側(cè)鏡 |
| 文件頁數(shù)： | 59/62頁 |
| 文件大?。?/td> | 540K |
| 代理商： | 908E621_07 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
59
908E621
ADDITIONAL INFORMATION
THERMAL ADDENDUM (REV 1.0)
Figure 35. Thermal Test Board
Device on Thermal Test Board
R
θ
JA
is the thermal resistance between die junction and
ambient air.
R
θ
JSmn
is the thermal resistance between die junction and
the reference location on the board surface near a center
lead of the package. This device is a dual die package. Index
m
indicates the die that is heated. Index
n
refers to the
number of the die where the junction temperature is sensed.
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
FLSVPP
PTA3/KBD3
PTA4/KBD4
VDDA/VREFH
EVDD
EVSS
VSSA/VREFL
(PTE1/RXD <- RXD)
VSS
VDD
HVDD
L0
H0
HS3
VSUP8
HS2
VSUP7
HS1b
HS1a
VSUP6
VSUP5
GND4
HB1
VSUP4
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
IRQ
RST
(PTD0/TACH0/BEMF -> PWM)
PTD1/TACH1
RST_A
IRQ_A
LIN
A0CST
A0
GND1
HB4
VSUP1
GND2
HB3
VSUP2
NC
NC
TESTMODE
GND3
HB2
VSUP3
1
2
3
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
9
10
6
7
8
4
5
54
53
52
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
46
45
49
48
47
51
50
EPad
908E621 Terminal Connections
54-Terminal SOICW-EP
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
A
Material:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
Outline:
80 mm x 100 mm board area,
including edge connector for
thermal testing
Area
A
:
Cu heat-spreading areas on board
surface
Ambient Conditions:
Natural convection, still air
Table 25. Thermal Resistance Performance
Thermal
Resistance
Area A
(mm
2
)
1 = Power Chip, 2 = Logic Chip
(
°
C/W)
m
= 1,
n
= 1
m
= 1,
n
= 2
m
= 2,
n
= 1
m
= 2,
n
= 2
R
θ
JA
mn
0
53
48
53
300
39
34
38
600
35
30
34
R
θ
JS
mn
0
21
16
20
300
15
11
15
600
14
9.0
13
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