參數(shù)資料
型號： 908E621_07
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror
中文描述： 綜合四半橋和三高的嵌入式微控制器和LIN高端側(cè)鏡
文件頁數(shù)： 3/62頁
文件大小： 540K
代理商： 908E621_07
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
908E621
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
Figure 3. Terminal Connections
Table 1. Terminal Definitions
A functional description of each terminal can be found in the
Functional Terminal Description
section beginning on page
21
.
Die
Terminal
Terminal Name
Formal Name
Definition
MCU
1
2
3
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
Port C I/Os
These terminals are special-function, bidirectional I/O port terminals
that are shared with other functional modules in the MCU.
MCU
4
5
6
PTB5/AD5
PTB4/AD4
PTB3/AD3
Port B I/Os
These terminals are special-function, bidirectional I/O port terminals
that are shared with other functional modules in the MCU.
MCU
7
IRQ
External Interrupt
Input
This terminal is an asynchronous external interrupt input terminal.
MCU
8
RST
External Reset
This terminal is bidirectional, allowing a reset of the entire system. It is
driven low when any internal reset source is asserted.
MCU /
Analog
9
(PTD0/TACH0/BEMF
-> PWM)
PWM signal
This terminal is the PWM signal test terminal. It internally connects the
MCU PTD0/TACH0 terminal with the Analog die PWM input.
Note: Do not connect in the application.
MCU
10
PTD1/TACH1
Port D I/Os
This terminal is a special-function, bidirectional I/O port terminal that is
shared with other functional modules in the MCU.
MCU /
Analog
44
(PTE1/RXD <- RXD)
LIN Transceiver
Output
This terminal is the LIN Transceiver output test terminal. It internally
connects the MCU PTE1/RXD terminal with the Analog die LIN
transceiver output terminal RXD.
Note: Do not connect in the application.
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
FLSVPP
PTA3/KBD3
PTA4/KBD4
VDDA/VREFH
EVDD
EVSS
VSSA/VREFL
(PTE1/RXD <- RXD)
VSS
VDD
HVDD
L0
H0
HS3
VSUP8
HS2
VSUP7
HS1b
HS1a
VSUP6
VSUP5
GND4
HB1
VSUP4
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
IRQ
RST
(PTD0/TACH0/BEMF -> PWM)
PTD1/TACH1
RST_A
IRQ_A
LIN
A0CST
A0
GND1
HB4
VSUP1
GND2
HB3
VSUP2
NC
NC
TESTMODE
GND3
HB2
VSUP3
1
2
3
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
9
10
6
7
8
4
5
54
53
52
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
46
45
49
48
47
51
50
Exposed
Pad
Transparent Top
View of Package
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