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參數(shù)資料
| 型號： | 908E621_07 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror |
| 中文描述： | 綜合四半橋和三高的嵌入式微控制器和LIN高端側(cè)鏡 |
| 文件頁數(shù)： | 44/62頁 |
| 文件大?。?/td> | 540K |
| 代理商： | 908E621_07 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
44
908E621
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
function is enabled it is not possible to disable it via software.
Reset clears the WDRE bit.
To prevent a Watchdog reset, the Watchdog timer has to
be cleared in the Window Open frame. This is done by writing
a logic “1” to the WDRST bit in the Watchdog Control register
(WDCTL). The actual reset of the watchdog counter occurs at
the end of the corresponding SPI transmission with the rising
edge of the SS
signal.
If the watchdog is enabled, it will generate a system reset
if the timer has reached its end value or if a watchdog reset
(WDRST) has occurred in the closed window.
The watchdog period can be selected with 2 bits in the
WDCTL, in order to get 10ms, 20ms, 40ms and 80ms period.
Figure 28. Window Watchdog Period
Stop mode
Operations of the watchdog function is ceased in stop
mode (counter/oscillator stopped). After wake-up the
watchdog timer
is automatically cleared
in order to give the
MCU the full time to reset the watchdog.
Sleep mode
Operations of the watchdog function is ceased is sleep
mode. Due to the reason that the main voltage regulator
asserts an LVR reset the Watchdog functionality is disabled
and the WDRE bit is cleared as soon as sleep mode is
entered. To reenable this function bit WDRE has to be set
after wake-up.
Watchdog Control Register (WDCTL)
WDRE - Watchdog Reset Enable Bit
This read/write (write once) bit activates the watchdog The
WDRE can only be set and can not be cleared by software.
Reset
clears the WDRE bit.
1 = Watchdog enabled
0 = Watchdog disabled
WDP1:0 - Watchdog Period Select Bits
This read/write bit select the clock rate of the Watchdog.
Reset clears the WDP1:0 bits.
Table 12. Watchdog Period Selection Bits
WDRST - Watchdog Reset Bit
This write only bit resets the Watchdog. Write a logic [1] to
reset the watchdog timer.
1 = Reset WD and restart timer
0 = no effect
Voltage Regulator
The 908E621
contains a low power, low drop voltage
regulator to provide internal power and external power for the
MCU. The on-chip regulator consist of two elements, the
main regulator and the low voltage reset circuit.
The V
DD
regulator accepts an unregulated input supply
and provides a regulated V
DD
supply to all digital sections of
the device. The output of the regulator is also connected to
the VDD terminal to provide the 5.0 V to the microcontroller.
Run mode
During RUN mode the main voltage regulator is on. It will
provide a regulated supply to all digital sections.
Window closed
no watch dog clear allowed
Window open
for watch dog clear
WD timing x 50%
WD timing x 50%
WD period ( timing selected by Bits WDP1:0)
Register Name and Address: WDCTL - $0B
Bit7
6
5
4
3
2
1
Bit0
Read
WDRE
WDP1
WDP0
0
0
0
0
0
Write
WDRST
Reset
0
0
0
0
0
0
0
0
WDP1
WDP0
Mode
0
0
80ms window watchdog period
0
1
40ms window watchdog period
1
0
20ms window watchdog period
1
1
10ms window watchdog period
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