參數(shù)資料
型號(hào)： 859S0424AGILF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 859S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封裝： 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
文件頁數(shù)： 5/18頁
文件大?。?/td> 1530K
代理商： 859S0424AGILF
ICS859S0424I
4:4, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
PRELIMINARY
IDT / ICS LVPECL/LVDS CLOCK MULTIPLEXER
13
ICS859S0424AGI REV. A MAY 18, 2007
LVPECL Clock Input Interface
The PCLK /PCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface
examples for the HiPerClockS PCLK/PCLK input driven by the
most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
Figure 2A. HiPerClockS PCLK/PCLK Input
Driven by an Open Collector CML Driver
Figure 2C. HiPerClockS PCLK/PCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2E. HiPerClockS PCLK/PCLK Input
Driven by an SSTL Driver
Figure 2B. HiPerClockS PCLK/PCLK Input
Driven by a Built-In Pullup CML Driver
Figure 2D. HiPerClockS PCLK/PCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
Figure 2F. HiPerClockS PCLK/PCLK Input
Driven by a 3.3V LVDS Driver
R1
50
R2
50
1.8V
Zo = 50
Zo = 50
CLK
nCLK
3.3V
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50
Zo = 50
PCLK
nPCLK
3.3V
LVPECL
HiPerClockS
Input
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
SSTL
2.5V
Zo = 60
Zo = 60
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
3.3V
R1
100
CML Built-In Pullup
PCLK
nPCLK
3.3V
HiPerClockS
PCLK/nPCLK
Zo = 50
Zo = 50
R3
84
R4
84
R1
125
R2
125
R5
100 - 200
R6
100 - 200
PCLK
nPCLK
3.3V LVPECL
3.3V
Zo = 50
Zo = 50
3.3V
HiPerClockS
PCLK/nPCLK
C1
C2
PCLK
nPCLK
3.3V
HiPerClockS
PCLK/nPCLK
R3
1k
R4
1k
R1
1k
R2
1k
3.3V
Zo = 50
Zo = 50
3.3V
C1
C2
R5
100
LVDS
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