參數(shù)資料
型號(hào): 859S0424AGILF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 859S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封裝: 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
文件頁(yè)數(shù): 4/18頁(yè)
文件大?。?/td> 1530K
代理商: 859S0424AGILF
ICS859S0424I
4:4, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
PRELIMINARY
IDT / ICS LVPECL/LVDS CLOCK MULTIPLEXER
12
ICS859S0424AGI REV. A MAY 18, 2007
Recommendations for Unused Input and Output Pins
Inputs:
PCLK/PCLK Inputs:
For applications not requiring the use of a differential input, both
the PCLK and PCLK pins can be left floating. Though not required,
but for additional protection, a 1k
resistor can be tied from PCLK
to ground.
LVCMOS Control Pins:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
Outputs:
LVPECL Outputs:
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVDS Outputs:
All unused LVDS output pairs can be either left floating or
terminated with 100
across. If they are left floating, there should
be no trace attached.
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