參數(shù)資料
型號(hào)： 859S0424AGILF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 859S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封裝： 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
文件頁(yè)數(shù)： 1/18頁(yè)
文件大小： 1530K
代理商： 859S0424AGILF
PRELIMINARY
4:4 DIFFERENTIAL-TO-LVPECL/LVDS
CLOCK MULTIPLEXER
ICS859S0424I
IDT / ICS LVPECL/LVDS CLOCK MULTIPLEXER
1
ICS859S0424AGI REV. A MAY 18, 2007
Description
The ICS859S0424I is a 4:4 Differential-to-LVPECL/
LVDS Clock Multiplexer which can operate up to
2.5GHz and is a member of the HiPerClockS
family of High Performance Clock Solutions from
IDT. The ICS859S0424I has 4 selectable differential
PCLKx/PCLKx clock inputs. The PCLKx/PCLKx input pairs can
accept LVPECL, LVDS, CML or SSTL levels. The fully differential
architecture and low propagation delay make it ideal for use in
clock distribution circuits. The select pins have internal pulldown
resistors. The CLK_SEL1 pin is the most significant bit and the
binary number applied to the select pins will select the same
numbered data input (i.e., 00 selects PCLK0, PCLK0).
Table 1A. VCC_TAP Function Table
Features
High speed 4:1 differential multiplexer with a 1:4 fanout buffer
Four differential LVPECL or LVDS output pairs
Four selectable differential PCLKx/PCLKx input pairs
PCLKx, PCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: 2.5GHz
Translates any single ended input signal to LVPECL levels with
resistor bias on PCLKx input
Part-to-part skew: TBD
Propagation delay: 555ps (typical)
Additive phase jitter, RMS: 0.16ps (typical)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Table 1B. SEL_OUT Function Table
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
Outputs
Output Level Supply
VCC_TAP
Qx[0:1]/Qx[0:1]
LVPECL
2.5V
VCC
LVPECL
3.3V
VCC
LVDS
2.5V
VCC
LVDS
3.3V
Float
HiPerClockS
ICS
Input
Outputs
SEL_OUT
Qx[0:1]/Qx[0:1]
1
LVPECL
0LVDS
ICS859S0424I
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Pin Assignment
Block Diagram
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK_SEL0
CLK_SEL1
PCLK0
PCLK1
PCLK2
PCLK3
OEA
OEB
VCC
VEE
QA0
QA1
QB0
QB1
VCC_TAP
SEL_OUT
QA0
PCLK0
CLK_SEL1
CLK_SEL0
OEA
OEB
PCLK0
PCLK1
PCLK2
PCLK3
0
1
0
1
QA1
QB0
QB1
Pullup/Pulldown
Pulldown
Pullup
SEL_OUT
Pullup
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
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