參數(shù)資料
型號(hào)： 859S0424AGILF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 859S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封裝： 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
文件頁(yè)數(shù)： 16/18頁(yè)
文件大?。?/td> 1530K
代理商： 859S0424AGILF
ICS859S0424I
4:4, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
PRELIMINARY
IDT / ICS LVPECL/LVDS CLOCK MULTIPLEXER
7
ICS859S0424AGI REV. A MAY 18, 2007
Table 6C. LVDS AC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at the differential cross points.
Table 6D. LVDS AC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, TA = -40°C to 85°C
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at the differential cross points.
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
3GHz
tPD
Propagation Delay; NOTE 1
550
ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.28
ps
tsk(b)
Bank Skew; NOTE 2, 3
35
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
TBD
ps
tR / tF
Output Rise/Fall Time
20% to 80%
220
ps
odc
Output Duty Cycle
50
%
MUXISOLATION MUX Isolation
OUT < 1.2GHz
45
dB
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
3GHz
tPD
Propagation Delay; NOTE 1
560
ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.29
ps
tsk(b)
Bank Skew; NOTE 2, 3
35
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
TBD
ps
tR / tF
Output Rise/Fall Time
20% to 80%
220
ps
odc
Output Duty Cycle
50
%
MUXISOLATION MUX Isolation
OUT < 1.2GHz
45
dB
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