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參數(shù)資料
| 型號： | 859S0424AGILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 859S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 1530K |
| 代理商： | 859S0424AGILF |
ICS859S0424I
4:4, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
PRELIMINARY
IDT / ICS LVPECL/LVDS CLOCK MULTIPLEXER
11
ICS859S0424AGI REV. A MAY 18, 2007
Parameter Measurement Information, continued
Differential Output Voltage Setup
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 1. Single-Ended Signal Driving Differential Input
100
out
LVDS
DC Input
VOD/ VOD
V
DD
Single Ended Clock Input
VCC
PCLKx
nPCLKx
R1
C1
0.1u
R2
1K
V_REF
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