參數資料
型號: 859S0424AGILF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 859S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封裝: 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
文件頁數: 17/18頁
文件大?。?/td> 1530K
代理商: 859S0424AGILF
ICS859S0424I
4:4, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
PRELIMINARY
IDT / ICS LVPECL/LVDS CLOCK MULTIPLEXER
8
ICS859S0424AGI REV. A MAY 18, 2007
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
have issues. Relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependant on the input source and measurement equipment.
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.16ps (typical)
SSB
Phase
Nois
e
dB
c/Hz
Offset Frequency (Hz)
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