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參數(shù)資料
| 型號： | 859S0424AGILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 859S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 1530K |
| 代理商： | 859S0424AGILF |
ICS859S0424I
4:4, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
PRELIMINARY
IDT / ICS LVPECL/LVDS CLOCK MULTIPLEXER
2
ICS859S0424AGI REV. A MAY 18, 2007
Table 2. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 3. Pin Characteristics
Number
Name
Type
Description
1,
2
CLK_SEL0,
CLK_SEL1
Input
Pulldown
Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels.
3
PCLK0
Input
Pulldown
Non-inverting differential LVPECL clock input.
4PCLK0
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
5
PCLK1
Input
Pulldown
Non-inverting differential clock input.
6PCLK1
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
7
PCLK2
Input
Pulldown
Non-inverting differential clock input.
8PCLK2
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
9
PCLK3
Input
Pulldown
Non-inverting differential clock input.
10
PCLK3
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
11
OEA
Input
Pullup
Output enable pin for Bank A outputs. See Table 4B.
LVCMOS/LVTTL interface levels.
12
OEB
Input
Pullup
Output enable pin for Bank B outputs. See Table 4B.
LVCMOS/LVTTL interface levels.
13
SEL_OUT
Input
Pullup
Output select pin. When LOW, selects LVPECL levels. When HIGH, selects
LVDS levels. LVCMOS/LVTTL interface levels. See Table 1B.
14
VCC_TAP
Power
Power supply pin. See Table 1A.
15, 16
QB1, QB1
Output
Differential output pair. LVPECL or LVDS interface levels.
17, 18
QB0, QB0
Output
Differential output pair. LVPECL or LVDS interface levels.
19, 20
QA1, QA1
Output
Differential output pair. LVPECL or LVDS interface levels.
21, 22
QA0, QA0
Output
Differential output pair. LVPECL or LVDS interface levels.
23
VEE
Power
Negative supply pin.
24
VCC
Power
Power supply pin.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN Input Pulldown Resistor
51
k
RVCC/2
Input Pullup/Pulldown Resistor
75
k
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