參數(shù)資料
型號: 8213AM
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 20/33頁
文件大?。?/td> 171K
代理商: 8213AM
SM8213AM
NIPPON PRECISION CIRCUITS—20
Miscellaneous Interface Pins
SIGNAL
NRZ-format signal input pin, with built-in noise can-
celler filter.
Current pager systems operate at 3 baud rates (512,
1200 and 2400 bps). In conventional systems, the RF
stage LPF time constants are changed in response to
the baud rate in order to get the best possible recep-
tion. However, this requires switching the external
components which results in increased product oper-
ating costs.
The SM8213AM, however, performs digital process-
ing on the input signal which allows the 3 baud rates
to be covered without the need to substitute RF stage
LPF components. The side effect of this digital filter
processing is a small probability of rate errors occur-
ring.
Digital processing can be turned ON/OFF using
flags. When turned ON, there are 4 filter constant set-
tings that can be selected to obtain the best possible
reception conditions in a flexible manner (see
“Parameter Flags” section).
XT, XTN
Crystal oscillator element connection pins.
The SM8213AM operates at 76.8 kHz system clock
speed, and this clock can be provided simply by con-
necting a crystal element between XT and XTN. The
oscillator amplifier, feedback resistance and oscilla-
tor capacitance are all built-in.
In this case, XTN should not be used as a clock to
drive an external device.
Also, a 1000 pF to 0.1 μF capacitor should be con-
nected between XVSS and VDD.
CLKO
Clock output pin. The clock output can be used as a
CPU sleep clock or melody IC (SM1124 series)
clock.
The output clock frequency, 76.8 or 38.4 kHz, is
selected using the decoder parameter set command.
RSTN
Decoder IC internal initialization reset pin. It also
functions as an oscillator start-up booster (current
source) immediately after power is applied to speed
up oscillator stabilization.
AREA
This pin goes HIGH for
1 second when a sync
code is detected with 2 or less random bit errors in
preamble, lock or idle mode sync code detection tim-
ing.
During intermittent-duty CPU operation, monitoring
this pin is useful for out-of-range signal strength.
However, even if a sync code is detected, this pin is
not held HIGH for
1 second if 2 consecutive sync
codes could not be detected, or under the following
situations in 1200 and 2400 bps modes.
I
When the second of 2 consecutive sync codes
could not be detected but a 6-bit preamble is
detected and preamble continues.
I
When operation transfers from lock mode to idle
mode and then to preamble mode. Note that if
operation stays in idle mode after transfer from
lock mode, this pin goes HIGH for
1 second.
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