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參數(shù)資料
| 型號： | 8213AM |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 12/33頁 |
| 文件大?。?/td> | 171K |
| 代理商： | 8213AM |
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SM8213AM
NIPPON PRECISION CIRCUITS—12
Preamble mode
Preamble mode is a continuous 544-bit long period.
If neither a preamble pattern, rate error nor sync code
is detected during this period, operation transfers to
idle mode.
If a preamble pattern is detected, the preamble mode
544-bit long period is recommenced.
If the sync code is detected, AREA goes HIGH and
operation transfers to lock mode. If an error of 2 bits
or less occurs, the detected word is recognized as the
sync code. During the preamble mode interval, BS1
and BS3 are held HIGH. BS2 stays LOW.
Note that a single error occurs when two active edges
occur in the received signal on SIGNAL within 1-bit
unit time. A rate error occurs when the number of
errors in the error counter equals the error threshold
set by flags ER0 to ER2. The error counter is reset
when a preamble pattern is detected.
Idle mode
In idle mode, a check is made for the presence of a
preamble signal when the RF intermittent-duty con-
trol signals (BS1, BS2, BS3) for battery saving are
active. If a preamble pattern is detected, operation
immediately transfers to preamble mode. If a pream-
ble pattern is not detected, intermittent-duty opera-
tion continues.
A preamble pattern is detected when either a 101010
or 010101 6-bit pattern is detected. Since there is a
reasonable probability that this simple pattern can
occur during a valid communicated signal (data, not
preamble), this 6-bit pattern makes returning to pre-
amble mode easier. This is useful for cases where
weak electric fields, noise or other temporary inter-
ference cause device operation to transfer to idle
mode.
Furthermore, the idle mode receive timing immedi-
ately after transfer from lock mode is the same as the
original sync code receive timing. As a result, if a
sync code is detected, operation returns to lock
mode.
Figure 5. Preamble mode internal operation
. . 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 . .
Preamble Signal
Preamble count
starts
Counting
Count reset to 0
Preamble detected
Preamble count restarts
Error bit
t
1 0 1 0 1 0 1
t : 1-bit time
t
t
t
t
t
t
Error counter (e. g. set value
≥
3)
0 1 1 1 2 2 0
Preamble and error
count starts
Preamble detected
and count reset
Figure 6. Idle mode timing
BS2
(flag BS2 option = 0)
BS1
62.5ms
(26.7ms)
[13.4ms]
Receive timing
1062.5ms (453.3ms) [226.7ms]
1.953*Nms
(0.833*Nms)
[0.417*Nms]
1.953*Mms
(0.833*Mms)
[0.417*Mms]
BS2
(flag BS2 option = 1)
BS3
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 8213B/13 | 制造商:WIELAND 功能描述:15 A, STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| 8213B/15VR | 制造商:Wieland 功能描述:15 A, STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| 8213B/20 | 制造商:WIELAND 功能描述:15 A, STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| 8213B/3-OB | 制造商:Wieland Electric Inc 功能描述: |
| 8213B/4 | 制造商:Wieland 功能描述:15 A, STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
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