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參數(shù)資料
| 型號： | 8213AM |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 171K |
| 代理商： | 8213AM |
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SM8213AM
NIPPON PRECISION CIRCUITS—14
Lock mode (dummy address setting is enabled)
If the sync code is detected during the preamble
period, device operation transfers to lock mode and
BS1 goes LOW. BS1 then goes HIGH again under
frame timing, where the frame number is set by flags
FF0 to FF2, and the 28 addresses and dummy
address are compared with ID-ROM (If the frame
number is 0, BS1 stays HIGH). If errors of 2 bits or
less occur in the 28 addresses, the address is still rec-
ognized. Since there are two code words per frame,
this check is done twice.
When all of the 28 addresses do not match, BS1 goes
LOW and the device waits for the next frame or sync
code receive timing. If the sync code is still not
detected after two consecutive attempts, device oper-
ation transfers to idle mode, except during message
reception where operation stays in lock mode. If the
sync code is not detected on the second attempt, but
instead a pattern forming a preamble is detected,
device operation transfers to preamble mode and not
idle mode (preamble mode is more advantageous for
sync code detection).
When one of the 28 addresses does match, ATTN
goes LOW and the 32-address information (see
“Data/Flags” section) is transmitted to the CPU on
SDO in sync with the SCK clock.
The dummy address is compared in the same way as
normal addresses, but regardless of the comparison
result after being compared in the assigned frame,
the dummy address is recognized as the device
address (even if it occurs within a message). It is
always recognized as the device address when it
appears in either the first or second code word of the
assigned frame. However, if addresses A to G are
used at the same time dummy addressing is enabled,
frames with dummy addresses should not be speci-
fied. If frames with a dummy address are specified,
the same frame will receive two addresses, and the
data transferred to the microcontroller will always be
the data corresponding to the dummy address, even
if one of the addresses is not a dummy address.
When the normal address and dummy address infor-
mation is confirmed to be a message, BS1 is held
HIGH and the message is received. The received
message is stored in a buffer as 32-bit error-corrected
information (see “Data/Flags” section), then ATTN
goes LOW and the data is transmitted to the CPU on
SDO in sync with the SCK clock.
When the address and message is received, ATTN
should be held LOW while the data is output on
SDO.
When an incoming message spans two or more
batches, additional sync code detection occurs dur-
ing sync code receive timing.
Message reception can be selected to end when
either an address code or idle code is detected, or
when interrupted using the decoder set command
BREAK input. This selection is made when setting
parameters that will not cause the message to termi-
nate. If the BREAK mode is selected, even if an
address other than the self address (MSB = 0) is
received during message reception, reception contin-
ues without interruption and address data is sent to
the microcontroller using the same data handling as
for a message. In this case, reception can only be
interrupted by a BREAK input signal from the
microcontroller.
Therefore, when dummy address (in combination
with normal addresses) handling is enabled and
parameters that will not cause the message to termi-
nate are selected, this means that the device can be
used in various radio and test equipment for business
applications.
In either of the above cases, message reception ends
if an end-of-message signal is sent. Note that if the
device address is received, the end-of-message data
is not transmitted.
When message reception ends, BS1 goes LOW and
the device waits for either the address detect timing
of the next frame or the sync code receive timing.
When sending data from the decoder to the micro-
controller, the SCK clock frequency should not be
less than 512, (1200), [2400] Hz. If this occurs, the
SCK counter is reinitialized. This function, however,
does make restoring operation easy even if this or
another clock is accidentally input.
Refer to figure 7 in the “Lock mode (dummy address
setting is disabled)” section.
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相關(guān)代理商/技術(shù)參數(shù) |
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| 8213B/13 | 制造商:WIELAND 功能描述:15 A, STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| 8213B/15VR | 制造商:Wieland 功能描述:15 A, STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
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| 8213B/3-OB | 制造商:Wieland Electric Inc 功能描述: |
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