參數(shù)資料
型號: 68HC05BD2
廠商: Motorola, Inc.
英文描述: 8-Bit Microcontroller Units (MCU).(8位微控制器)
中文描述: 8位微控制器單元(MCU)。(8位微控制器)
文件頁數(shù): 60/85頁
文件大?。?/td> 302K
代理商: 68HC05BD2
MOTOROLA
Page 50
SECTION 10: SYNC PROCESSOR
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
(BPOR=1)
corresponding polarity control bits, bit 3 and bit 2 of register $0C, can change the polarity
of
HSYNO
/
VSYNO
outputs. The result
HSYNO
and
VSYNO
outputs can vary while the
setting in
SPCSR
and
SPIOCR
register is different. If the
COMP
bit in
SPCSR
register is
set, the incoming composite Sync signal will be the HSYNO output and the extracted
VSYNC with 6~7us delay will be the VSYNC output. When the
SOUT
bit in
SPIOCR
register is set, the internal free-running
55.556KHz
with 2us pulse will be the
HSYNO
output and the other free-running
72.34Hz
with 108us pulse will be the
VSYNO
output.
10.2.4
CLAMP Pulse Output
The logic will generate a 0.5us - 0.75us pulse at either the leading edge or the trailing edge
which is specified by the
BPOR
bit in the
SPIOCR
register. See
Figure 10-1
for its detail
timing relation. One control bit to invert the output polarity of CLAMP pulse is located at bit
5 of
SPIOCR
.
Figure 10-1: CLAMP output waveform
HSYNC
(HPOL=1)
CLAMP
(BPOR=0)
CLAMP
(BPOR=1)
HSYNC
(HPOL=0)
CLAMP
(BPOR=0)
CLAMP
0.5-0.75us
0.5-0.75us
0.5-0.75us
0.5-0.75us
0.5-0.75us
0.5-0.75us
0.5-0.75us
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相關(guān)代理商/技術(shù)參數(shù)
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