參數(shù)資料
型號(hào)： 68HC05BD2
廠商： Motorola, Inc.
英文描述： 8-Bit Microcontroller Units (MCU).(8位微控制器)
中文描述： 8位微控制器單元（MCU）。（8位微控制器）
文件頁(yè)數(shù)： 54/85頁(yè)
文件大?。?/td> 302K
代理商： 68HC05BD2
MOTOROLA
Page 44
SECTION 9: DDC12AB INTERFACE
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
downloaded to the shift register until next calling from master (
TXBE
remains unchanged).
TXBE
Bit 1
The Transmit Buffer Empty (TXBE) flag indicates the status of
the DDTR register. When the cpu writes the data into the
DDTR register, the TXBE flag will be cleared. And it will be set
again after the data of the DDTR register has been loaded to
the shift register. It is default to be set when the DEN is
disable and will be cleared by writing data to the DDTR
register when the DEN is enabled.
The Receive Buffer Full (RXBF) flag indicates the status of the
DDRR register. When the cpu reads the data from the DDRR
register, the RXBF flag will be cleared. And it will be set after
the data or matched address is transferred from the shift
register to the DDRR register. It is cleared when DEN is
disabled or DDRR register is read when DEN is enabled.
RXBF
Bit 0
9.3.5
DDC Data Transmit Register (DDTR)
The data written into this register after
DEN
is enabled will be automatically downloaded to
the shift register when the module detects the calling address is matched and the bit 0 of
the received data is one or when the data in the shift register has been transmitted with
received acknowledge bit,
RXAK
=0. So if the program doesn’t write the data into the
DDTR
register (
TXBE
is cleared) before the matched calling address is detected, the module will
pull down the
SCL
line. If the cpu write a data to the
DDTR
register, then the written data
will be downloaded to the shift register immediately and the module will release the SCL
line, then the
TXBE is
set again and the
TXIF
flag is set to generate another interrupt
request for data. So the cpu may need to write the next data to the
DDTR
register to clear
TXBE
flag and for the auto downloading of data to the shift register after the data in the shift
register is transmitted over again with
RXAK
=0. If the master receiver doesn’t acknowledge
the transmitted data,
RXAK
=1, the module will release the
SDA
line for master to generate
’stop’ or ’repeated start’ conditions. The data stored in the
DDTR
register will not be
9.3.6
DDC Data Receive Register (DDRR)
The
DDC
Data Receive Register (
DDRR
) contains the last received data when the MATCH
flag is zero or the calling address from master when the
MATCH
flag is one. The
DDRR
register will be updated after a data byte is received and the
RXBF
is zero. It is a read-only
register. The read operation of this register will clear the
RXBF
flag. After the
RXBF
flag is
DTD7
1
7
DTD0
1
1
1
1
1
1
1
6
5
4
3
2
1
0
DTD4
W
R
DDTR
$001A
reset
DTD5
DTD6
DTD2
DTD3
DTD1
DRD7
0
7
DRD0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
DRD4
W
R
DDRR
$001B
reset
DRD5
DRD6
DRD2
DRD3
DRD1
相關(guān)PDF資料
PDF描述
68HC05BD7 8-Bit Microcontroller Units (MCU).(8位微控制器)
68HC705BD7 8-Bit Microcontroller Units (MCU).(8位微控制器)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
68HC05BD7 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SPECIFICATION REV 2.0 (General Release)
68HC05C0FN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
68HC05C0P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
68HC05C4AFB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
68HC05C4AFN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
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