參數(shù)資料
型號: 68HC05BD2
廠商: Motorola, Inc.
英文描述: 8-Bit Microcontroller Units (MCU).(8位微控制器)
中文描述: 8位微控制器單元(MCU)。(8位微控制器)
文件頁數(shù): 55/85頁
文件大?。?/td> 302K
代理商: 68HC05BD2
SECTION 9: DDC12AB INTERFACE
MOTOROLA
Page 45
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
MATCH=1
SRW=0
cleared, the register can load the received data again and set the
RXIF
flag to generate
interrupt request for reading the newly received data.
9.4
Data Sequence
9.5
Program Algorithm
The
Figure 9-1
shows the algorithm of slave mode interrupt routine of DDC12B protocol.
The
Figure 9-2
shows the algorithm of master mode setup and interrupt service routine.
When the DDC module detects an arbitration loss in master mode, it will release both SDA
and SCL lines immediately. But if there is no further "stop condition" detected, the module
will be hanged up. So it is recommended to have time-out software to recover from such ill
condition. The software can start the time-out counter by looking at the BB (Bus Busy) in
the bit 5 of DMCR and reset the counter when the completion of one byte transmission. If
the time-out occurred, program can clear DEN bit to release the bus, and then set DEN bit
START Address 0
ACK
TX Data1
ACK
TX DataN
NAK
STOP
TXBE=0
MAST=1
MRW=0
TXIF=1
TXBE=1
TXIF=1
TXBE=1
NAKIF=1
MAST=0
TXBE=0
START Address 1
ACK
RX Data1
ACK
RX DataN
NAK
STOP
RXBF=0
MAST=1
RXIF=1
RXBF=1
RXIF=1
RXBF=1
NAKIF=1
MAST=0
START Address 1
ACK
TX Data1
ACK
TX DataN
NAK
STOP
TXBE=0
RXBF=0
RXIF=1
RXBF=1
TXiF=1
TXBE=1
MATCH=1
SRW=1
TXIF=1
TXBE=1
START Address 0
ACK
RX Data1
ACK
RX DataN
NAK
STOP
TXBE=0
RXBF=0
RXIF=1
RXBF=1
RXIF=1
RXBF=1
RXIF=1
RXBF=1
a) Master Transmit mode
b) Master Receive mode
c) Slave Transmit mode
d) Slave Receive mode
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