- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369230 > 68HC05BD2 (Motorola, Inc.) 8-Bit Microcontroller Units (MCU).(8位微控制器) PDF資料下載
參數(shù)資料
| 型號： | 68HC05BD2 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 51/85頁 |
| 文件大小： | 302K |
| 代理商： | 68HC05BD2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當(dāng)前第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
SECTION 9: DDC12AB INTERFACE
MOTOROLA
Page 41
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELMNARY
Bit 6
The No AcKnowledge Interrupt Flag is only set in master
mode when there is no acknowledge bit detected after one
data byte or calling address is transferred. This bit can
generate an interrupt request to cpu when the DIEN bit in
DCR register is set and I-bit in the Condition Code Register is
clear. This bit is cleared by writing ’0’ to it or by reset.
Bit 5
The Bus Busy Flag is set after a start condition is detected,
and is reset when a stop condition is detected. This bit can
supplement the software in initiating the master mode
protocol. Reset clears this bit.
TXAK
Bit 3
If the transmit acknowledge enable bit (TXAK) is cleared, an
acknowledge signal will be sent out to the bus at the 9th clock
bit after receiving 8 data bits. When TXAK is set, no
acknowledge signal will be generated at the 9th clock (i.e.,
acknowledge bit = 1). Reset clears this bit.
If the SCL Interrupt ENable bit (SCLIEN) is set, the interrupt
occurs provided the SCLIF in the status register is set and the
I-bit in the Condition Code Register is cleared. If SCLIEN is
cleared, the interrupt of SCLIF is disabled. Reset clears this
bit.
When DDC1 protocol ENable (DDC1EN) is set, the VSYNC
edge will continuously clock out the data in the shift register.
No calling address comparison is performed. The RW bit in
the status register will be fixed to be one. If this bit is clear, the
SCLIF bit in the status register is also cleared. Reset clears
this bit.
SCLIEN
Bit 2
DDC1EN
Bit 1
9.3.3
DDC Master Control Register (DMCR)
The DMCR contains two interrupt flags, one bus status flag, two master mode control bits,
and three baudrate select bits.
ALIF
Bit 7
The Arbitration Loss Interrupt Flag is set when software
attempt to set MAST but the BB has been set by detecting the
start condition on the lines or when the DDC12AB module is
transmitting a ’one’ to SDA line but detected a ’zero’ from SDA
line in master mode, which is so called arbitration loss. This
bit can generate an interrupt request to cpu when the DIEN bit
in DCR register is set and I-bit in the Condition Code Register
NAKIF
BB
0
7
0
0
0
0
0
0
0
6
5
4
3
2
1
0
W
DMCR
$0016
reset
MRW
ALIF
NAKIF
BR2
BR1
BB
MAST
BR0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 68HC05BD7 | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC705BD7 | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC05J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC705J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HRC05J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 68HC05BD7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SPECIFICATION REV 2.0 (General Release) |
| 68HC05C0FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C0P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C4AFB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C4AFN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。