參數(shù)資料
型號： 440GR
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GR Embedded Processor
中文描述： 440GR的Power PC嵌入式處理器
文件頁數(shù)： 77/82頁
文件大?。?/td> 527K
代理商： 440GR
AMCC Proprietary
79
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Revision 1.16 – July 19, 2006
Initialization
The PPC440GR provides the option for setting initial parameters based on default values or by reading them from
a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered
by strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440GR start-up. The actual capture instant is the nearest reference clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. These pins are used for strap functions only during reset.
Following reset they are used for normal functions. The signal names assigned to the pins for normal operation are
shown in parentheses following the pin number.
The following table lists the strapping pins along with their functions and strapping options:
Serial EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device
connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440GR
sequentially reads 16B from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1,
SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly.
The initialization settings and their default values are covered in detail in the PowerPC 440GR User’s Manual.
Table 24. Strapping Pin Assignments
Function
Option
Ball Strapping
R25
(UART0_DCD)
U26
(UART0_DSR)
V26
(UART0_CTS)
Serial device is disabled. Each of the six options (A–
F) is a combination of boot source, boot-source
width, and clock frequency specifications. Refer to
the IIC Bootstrap Controller chapter in the
PPC440GR Embedded Processor User’s Manual for
details.
A
000
B
001
C
010
D
011
E
100
F
110
Serial device is enabled. The option being selected is
the IIC0 slave address that will respond with
strapping data.
Note: If reading of configuration data from the serial
device fails, the PPC440GR defaults to configuration
X.
G (0xA8)
101
H (0xA4)
111
相關(guān)PDF資料
PDF描述
440GX Power PC 440GX Embedded Processor
440SPE PowerPC 440SPe Embedded Processor
440SP PowerPC 440SP Embedded Processor
4414-308 8 POS SOIC ADAPTER
4414-308LF 8 POS SOIC ADAPTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
440GRX 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440GRx Embedded Processor
440GS001NF1934-4 功能描述:環(huán)形MIL規(guī)格后蓋 CRIMIP RING ADPTR DC STRAIGHT RoHS:否 制造商:Amphenol PCD MIL 類型:MIL-DTL-38999 III, IV 系列:AS85049 產(chǎn)品類型:Environmental EMI/RFI Backshells 外殼類型:Straight 外殼大小:18 外殼材質(zhì):Aluminum Alloy
440GS001NF2535-4 功能描述:環(huán)形MIL規(guī)格后蓋 CRIMIP RING ADPTR DC STRAIGHT RoHS:否 制造商:Amphenol PCD MIL 類型:MIL-DTL-38999 III, IV 系列:AS85049 產(chǎn)品類型:Environmental EMI/RFI Backshells 外殼類型:Straight 外殼大小:18 外殼材質(zhì):Aluminum Alloy
440GS031B2912-4 制造商:Glenair Inc 功能描述:Shrink Boot Adapters 180° 29 Shell Size Olive Drab Cadmium Aluminum Direct 制造商:Glenair 功能描述:Shrink Boot Adapters 180° 29 Shell Size Olive Drab Cadmium Aluminum Direct
440GS031B3314-4 制造商:Glenair Inc 功能描述:Shrink Boot Adapters 180° 33 Shell Size Olive Drab Cadmium Aluminum Direct 制造商:Glenair 功能描述:Shrink Boot Adapters 180° 33 Shell Size Olive Drab Cadmium Aluminum Direct
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*