參數(shù)資料
型號(hào)： 440GR
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GR Embedded Processor
中文描述： 440GR的Power PC嵌入式處理器
文件頁(yè)數(shù)： 70/82頁(yè)
文件大小： 527K
代理商： 440GR
72
AMCC Proprietary
Revision 1.16 – July 19, 2006
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
DDR SDRAM Write Operation
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 8. DDR SDRAM Write Cycle Timing
DQS
MemData
PLB Clk
MemClkOut0
MemClkOut0(90)
Addr/Cmd
TSK
TSA
THA
TDS
TSD
THD
TSD
THD
TSA = Setup time for address and command signals to MemClkOut0(90)
TSK = Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)
THA = Hold time for address and command signals from MemClkOut0(90)
TDS = Delay from rising/falling edge of clock to the rising/falling edge of DQS
TSD = Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
THD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
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參數(shù)描述
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