參數(shù)資料
型號(hào)： 440GR
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GR Embedded Processor
中文描述： 440GR的Power PC嵌入式處理器
文件頁(yè)數(shù)： 71/82頁(yè)
文件大?。?/td> 527K
代理商： 440GR
AMCC Proprietary
73
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Revision 1.16 – July 19, 2006
Note:
The timing data in the following tables is based on simulation runs using Einstimer.
Table 20. I/O Timing—DDR SDRAM TDS
Notes:
1. All of the DQS signals are referenced to MemClkOut0(0).
2. Clock speed is 133MHz.
3. The TDS values in the table include 3/4 of a cycle at 133MHz (7.5ns x 0.75 = 5.625 ns).
4. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle
time for the lower clock frequency (TDS - 5.625 + 0.75TCYC).
Signal Name
TDS (ns)
Minimum
Maximum
DQS0
5.76
5.86
DQS1
5.78
5.91
DQS2
5.82
5.90
DQS3
5.79
5.89
DQS8
5.75
5.88
Table 21. I/O Timing—DDR SDRAM TSK, TSA, and THA
Notes:
1. Clock speed is 133MHz. TSK is referenced to MemClkOut0(0). TSA and THA are referenced to MemClkOut0(90).
2. To obtain adjusted TSA values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and subtract
TSK maximum (0.75TCYC - TSKmax).
3. To obtain adjusted THA values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add
TSK minimum (0.25TCYC + TSKmin).
Signal Name
TSK (ns)
TSA (ns)
THA (ns)
MinimumMaximumMinimum
Minimum
MemAddr00:12
0.11
0.32
5.31
1.99
BA0:1
0.07
0.31
5.32
1.95
BankSel0:3
0.05
0.25
5.38
1.93
ClkEn0:3
0.07
0.28
5.35
1.95
CAS
0.05
0.31
5.32
1.93
RAS
0.05
0.28
5.35
1.93
WE
0.08
0.22
5.41
1.96
Table 22. I/O Timing—DDR SDRAM TSD and THD
Notes:
1. TSD and THD are measured under worst case conditions.
2. Clock speed for the values in the table is 133MHz.
3. The time values in the table include 1/4 of a cycle at 166MHz (7.5ns x 0.25 = 1.875 ns).
4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.875 ns from the values in the table and add
1/4 of the cycle time for the lower clock frequency (e.g., TSD - 1.875 + 0.25TCYC).
Signal Names
Reference Signal
TSD (ns)
THD (ns)
MemData00:07, DM0
DQS0
1.795
1.866
MemData08:15, DM1
DQS1
1.775
1.865
MemData16:23, DM2
DQS2
1.745
1.862
MemData24:31, DM3
DQS3
1.765
1.864
ECC0:7, DM8
DQS8
1.685
1.857
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