參數(shù)資料
型號： 440GR
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GR Embedded Processor
中文描述： 440GR的Power PC嵌入式處理器
文件頁數(shù)： 76/82頁
文件大小： 527K
代理商： 440GR
78
AMCC Proprietary
Revision 1.16 – July 19, 2006
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
Example 3:
In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system
will still work, but there will be more latency before the data is sampled into RDSP. In this example, TT and TTE are
controlled and set by the software.
Figure 13. DDR SDRAM Read Cycle Timing—Example 3
DQS at pin
PLB Clock
Read Clock Delayed
TSIN
Data at pin
D0
D1
D2
D3
DQS Stage 1 C
D0
D1
D2
D3
TDIN
D0
D2
Data in Stage 1 D
D1
D3
Data out Stage 1
High
Low
TP
D0
D2
D1
D3
Data out Stage 3
High
Low
with ECC
TT = Propagation delay from Stage 2 input to RDSP input w/o ECC
D0
D2
D1
D3
Data out Stage 2
High
Low
Data out RDSP
High
Low
(3)
with ECC
TP
D0
D2
D1
D3
Data in at RDSP
High
Low
with ECC
D0
D2
D1
D3
TTE = Propagation delay from Stage 2 input to RDSP input with ECC
TTE
D0
D2
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參數(shù)描述
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