參數(shù)資料
型號(hào)： 440GR
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GR Embedded Processor
中文描述： 440GR的Power PC嵌入式處理器
文件頁(yè)數(shù)： 47/82頁(yè)
文件大?。?/td> 527K
代理商： 440GR
AMCC Proprietary
51
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Revision 1.16 – July 19, 2006
DDR SDRAM Interface
BA0:1
Bank Address supporting up to four internal banks.
O
2.5V SSTL_2
BankSel0:3
Selects up to four external DDR SDRAM banks.
O
2.5V SSTL_2
CAS
Column Address Strobe.
O
2.5V SSTL_2
ClkEn
Clock Enable.
O
2.5V SSTL_2
DM0:3
DM8
Memory write data byte lane masks. DM8 is the byte lane
mask for the ECC byte lane.
O
2.5V SSTL_2
DQS0:3
DQS8
Byte lane data strobe. DQS8 is the data strobe for the ECC
byte lane.
I/O
2.5V SSTL_2
ECC0:7
ECC check bits 0:7.
I/O
2.5V SSTL_2
MemAddr00:12
Memory address bus.
O
2.5V SSTL_2
MemClkOut0
Subsystem clock.
O
2.5V SSTL_2
Diff driver
MemData00:31
Memory data bus.
I/O
2.5V SSTL_2
MemSelfRef
Self refresh.
I
3.3V tolerant
2.5V CMOS
5
RAS
Row Address Strobe.
O
2.5V SSTL_2
WE
Write Enable.
O
2.5V SSTL_2
SVREF1
SSTL reference voltage.
I
Volt ref receiver
SVREF2A:B
Supplemental SSTL reference voltage.
I
Volt ref pin
(supplemental)
Table 7. Signal Functional Description (Sheet 2 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω to 3.3V)
3. Must pull down (recommended value is 1k
Ω)
4. If not used, must pull up (recommended value is 3k
Ω to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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參數(shù)描述
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