參數(shù)資料
型號： 440GR
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GR Embedded Processor
中文描述： 440GR的Power PC嵌入式處理器
文件頁數(shù)： 55/82頁
文件大?。?/td> 527K
代理商： 440GR
AMCC Proprietary
59
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Revision 1.16 – July 19, 2006
Table 9. Recommended DC Operating Conditions (Sheet 1 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
Logic Supply Voltage
VDD
+1.4
+1.5
+1.6
V
4
I/O Supply Voltage
OVDD
+3.0
+3.3
+3.6
V
4
SDRAM Supply Voltage
SVDD
+2.3
+2.5
+2.7
V
4
PLL Supply Voltages
AVDD
+1.4
+1.5
+1.6
V
3, 4
SDRAM PLL Voltage
SAVDD
+1.4
+1.5
+1.6
V
3, 4
DDR SDRAM Reference Voltage
SVREF
+1.15
+1.25
+1.35
V
2
Input Logic High (2.5V SSTL)
VIH
SVREF+0.18
SVDD+0.3
V
Input Logic High (2.5V CMOS, 3.3V tolerant receiver)
1.7
???
V
Input Logic High (3.3V PCI)
0.5OVDD
OVDD+0.5
V1
Input Logic High (3.3V LVTTL)
+2.0
+3.6
V
Input Logic Low (2.5V SSTL)
VIL
-0.3
SVREF-0.18
V
Input Logic Low (2.5V CMOS, 3.3V tolerant receiver)
???
0.7
V
Input Logic Low (3.3V PCI)
-0.5
0.35OVDD
V1
Input Logic Low (3.3V LVTTL)
0
+0.8
V
Output Logic High (2.5V SSTL)
VOH
+1.95
SVDD
V
Output Logic High (2.5V CMOS, 3.3V tolerant receiver)
2.0
???
V
Output Logic High (3.3V PCI)
0.9OVDD
OVDD
V1
Output Logic High (3.3V LVTTL)
+2.4
OVDD
V
Output Logic Low (2.5V SSTL)
VOL
00.55
V
Output Logic Low (2.5V CMOS, 3.3V tolerant receiver)
0.4
V
Output Logic Low (3.3V PCI)
0.1OVDD
V1
Output Logic Low (3.3V LVTTL)
0
+0.4
V
Input Leakage Current (No pull-up or pull-down)
IIL1
00
μA
Input Leakage Current for Pull-Down
IIL2
0 (LPDL)
200 (MPUL)
μA
Input Leakage Current for Pull-Up
IIL3
-150 (LPDL)
0 (MPUL)
μA
Input Max Allowable Overshoot (3.3V LVTTL)
VIMAO
+3.9
V
Input Max Allowable Undershoot (3.3V LVTTL)
VIMAU
-0.6
V
Output Max Allowable Overshoot (3.3V LVTTL)
VOMAO
+3.9
V
Output Max Allowable Undershoot (3.3V LVTTL)
VOMAU3
-0.6
V
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