參數(shù)資料
型號(hào)： 440GR
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GR Embedded Processor
中文描述： 440GR的Power PC嵌入式處理器
文件頁(yè)數(shù)： 6/82頁(yè)
文件大小： 527K
代理商： 440GR
14
AMCC Proprietary
Revision 1.16 – July 19, 2006
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
Serial Peripheral Interface (SPI/SCP)
The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous,
character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on
the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.
Features include:
Three-wire serial port interface
Full-duplex synchronous operation
SCP bus master
OPB bus slave
Programmable clock rate divider
Clock inversion
Reverse data
Local data loop back for test
NAND Flash Controller
The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND
Flash devices. It provides both direct command, address, and data access to the external device as well as a
memory-mapped linear region that generates data accesses. NAND Flash device data appears on the peripheral
data bus.
Features include:
1 to 4 banks supported on EBC
Direct Interfacing to:
– Discrete NAND Flash devices (up to 4 devices)
– SmartMedia Card socket (22-pins)
Device sizes 4MB–256MB supported
(512 + 16)-B or (2K + 64)-B device page sizes supported
Boot-from-NAND: Execute a linear sequence of boot code out of single page of first block (512B)
Support DMA to allow direct, no-processor-intervention block copy from NAND Flash to SDRAM
ECC provides single-bit error correction and double-bit error detection in each 256B of stored data
Chip selects shared with EBC
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor
core.
Features include:
32-bit Time Base Counter driven by the OPB bus clock
Seven 32-bit compare timers
General Purpose IO (GPIO) Controller
Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master
accesses.
64 GPIOs are multiplexed with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose.
Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,
tri-stated if output bit is 1).
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