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參數(shù)資料
| 型號： | 34C60 |
| 廠商： | SMSC Corporation |
| 英文描述： | PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE |
| 中文描述： | 并行接口芯片外設(shè)端 |
| 文件頁數(shù)： | 49/58頁 |
| 文件大?。?/td> | 350K |
| 代理商： | 34C60 |
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SMSC DS – PPC34C60
Page 53
Rev. 06/01/2001
ADVANCED INFORMATION
FIGURE 23 - DRAM READ CYCLE TIMING
When the DRAM bus width (4, 8 or 16 bits) is narrower than the Host bus (always 8-bits) or the Peripheral bus (8 or 16 bits)
than the PPC34C60 will implement fast page mode DRAM cycles to complete the data transfer. These page mode
transfers are performed for DMA as well as Host DRAM access.
See DRAM Read Cycle Timing Parameters.
DRAM READ CYCLE TIMING
PARAMETER
MIN
TYP
MAX
UNITS
t1
10-bit DRAM row address valid to nRD asserted.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t2
10-bit DRAM row address valid to nRAS asserted.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t3
nRAS asserted to valid 10-bit DRAM column
address.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t4
10-bit DRAM column address valid to nCAS
asserted.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t5
10-bit DRAM column address incremented and at the
same time the data is latched into the PPC34C60
following nCAS asserted.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t6
nCAS deasserted after the column address has been
updated and the data has been latched by the
PPC34C60.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t7
nCAS deasserted pulse width during page mode
accesses.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t8
nCAS asserted to valid data, i.e., maximum
acceptable DRAM access time.
0
74
[1BCLK
-10]
ns
t9
nCAS deasserted to DRAM releasing data from the
bus.
0
74
[1BCLK
-10]
ns
t10
nCAS and nRAS both deasserted to nRD
deasserted.
0
42
[1 SCLK]
ns
t3
t5
t4
t6
t7
t6
t2
t1
t10
t8
t9
t8
t9
Data Valid
Row Addr
Col Addr
Col Addr +2
Col Addr +1
SAB
Data Valid
Col Addr bits 8 & 9
SAB
MA[8:9]
SA[0:7]
nCAS
nRAS
nRD
nWR
SD[0:15]
BUSCLK
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