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參數(shù)資料
| 型號(hào)： | 34C60 |
| 廠商： | SMSC Corporation |
| 英文描述： | PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE |
| 中文描述： | 并行接口芯片外設(shè)端 |
| 文件頁數(shù)： | 11/58頁 |
| 文件大?。?/td> | 350K |
| 代理商： | 34C60 |
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SMSC DS – PPC34C60
Page 19
Rev. 06/01/2001
ADVANCED INFORMATION
4
REGISTER DESCRIPTIONS
ADDRESS REGISTER - 0000 (Read/Write)
The value in the Address Register represents the current address presented to the Bus Address lines SA[0:7]. The primary
method of updating this value is the following sequence. First the Address Register is selected to be written to by
performing an Address Write operation (XWBMA3A2A1A0=x1110000). Next a Data Write operation is issued to write
A<0:7> as a group equal to the value presented on the parallel port host data lines HD[0:7].
A shorthand mode is also provided to allow the Address to be modified and Bus Operation to be selected in one Address
Write operation. If B = 0, then bus operation is selected and A3A2A1A0 is written to A<0-3>; A<4-7> are unaffected. In
this mode, if M = 1, then the bus access will be limited by the Host Max Block Count Register. Any attempts to read more
data will return invalid data. The PPC34C60 contains an integrated FIFO to enhance performance by reading the Bus one
or two bytes ahead of the Host Port. As an example, some devices such as IDE hard drives expect data to be read in a
fixed block length (sector). Set MAXCNT (Configuration Register bit 6) and set the value of Host Max Block Count Register
to the length of the IDE data block to read only the desired amount of data (1 sector) from the peripheral.
If M = 0, then the current setting of MAXCNT and Host Max Block Count are ignored. This allows polling of a status
register without limiting the number of times the register may be accessed.
The PPC34C60 directly provides eight address lines. If more than eight bits of address are necessary, three strobe lines
are available which may be used with external circuitry to latch higher-order address bits off of SA[0:7]. For example, the
address register can be written with higher order address bits and latched with one or more of the three programmable
strobe lines. The address register is then written with A0-A7, and normal bus reads/writes follow. This scheme may be
extended to any size address bus needed.
An auto-increment option may be activated by setting AUTOINC (bit 4 in the Operation Register, RRRR=0100) which will
increment A<0:7> after each bus access.
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