參數(shù)資料
型號： 34C60
廠商： SMSC Corporation
英文描述： PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE
中文描述： 并行接口芯片外設(shè)端
文件頁數(shù)： 18/58頁
文件大?。?/td> 350K
代理商： 34C60
SMSC DS – PPC34C60
Page 25
Rev. 06/01/2001
ADVANCED INFORMATION
HOST DRAM BUFFER POINTER REGISTER - 0110 (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HOST DRAM BUFFER POINTER (0-255)
This register sets the Host's DRAM pointer to the selected buffer. The DRAM address is calculated using this pointer, the
DRAM Buffer Size Register, and the DRAM bus width from the Configuration Register. If MAXCNT is set during the Host to
DRAM transfer, then this register is incremented upon reaching maximum count, and the DRAM address is recalculated for
the next buffer.
A maximum of 256 buffers are available in this register. The actual number of buffers depends on the DRAM loaded, and
the buffer size selected. If the pointer is incremented past the last buffer, it will wrap back around to the first buffer. No
active buffer count is maintained; the driver software must prevent overwriting existing buffers.
DMA DRAM BUFFER POINTER REGISTER - 0111 (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMA DRAM BUFFER POINTER (0-255)
This register sets the DMA DRAM pointer to the selected buffer. Its operation is similar to the Host DRAM Buffer
Pointer Register. This register is incremented upon completion of a DMA transfer and the DRAM address is recalculated
for the next buffer.
HOST MAX BLOCK BYTE-COUNT LOW REGISTER - 1000 (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HOST MAX BLOCK BYTE-COUNT LOW (HBC[7:0])
This register sets the low byte of the counter for Host block transfers. It is used in conjunction with MAXCNT in the
Configuration register to limit external DRAM and bus read accesses. The counter is reloaded with this value at every
Address Write cycle.
HOST MAX BLOCK BYTE-COUNT HIGH REGISTER - 1001 (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HOST MAX BLOCK BYTE-COUNT HIGH (HBC[15:8])
This register sets the high byte of the counter for Host block transfers. It is used in conjunction with MAXCNT in the
Configuration register to limit external DRAM and bus read accesses. The counter is reloaded with this value at every
Address Write cycle.
DMA BYTE-COUNT LOW REGISTER - 1010 (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMA BYTE-COUNT LOW (DBC[7:0])
This register sets the low byte of the 16-bit byte counter used for terminating DMA transfers. Subsequent DMA transfers
with the same byte count can be kicked off by resetting the DMA Enable bit in the Operation Register.
DMA BYTE-COUNT HIGH REGISTER - 1011 (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMA BYTE-COUNT HIGH (DBC[15:8])
This register sets the high byte of the 16-bit byte counter used for terminating DMA transfers. Subsequent DMA transfers
with the same byte count can be kicked off by resetting the DMA Enable bit in the Operation Register.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
34C7561 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DESIGN CENTER
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34C7565 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PLCC 84 BREAKOUT ADAPTER BRD
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