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參數(shù)資料
| 型號(hào)： | 34C60 |
| 廠商： | SMSC Corporation |
| 英文描述： | PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE |
| 中文描述： | 并行接口芯片外設(shè)端 |
| 文件頁(yè)數(shù)： | 41/58頁(yè) |
| 文件大?。?/td> | 350K |
| 代理商： | 34C60 |
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SMSC DS – PPC34C60
Page 46
Rev. 06/01/2001
ADVANCED INFORMATION
FIGURE 17 - EPP DATA READ TIMING (PARALLEL PORT SIGNALS)
See EPP Data Read Timing Parameters.
EPP DATA READ TIMING (PARALLEL PORT SIGNALS)
PARAMETER
MIN
TYP
MAX
UNITS
t1
The Host deasserts nSTB to indicate that
the forthcoming transfer is a read cycle. At
the same time or soon after the Host will
release the Parallel port data lines HD[0:7]
to a high impedance state. This specifies
the time between nSTB being asserted and
an address appearing on HD[0:7].The
PPC34C60 does not rely on nSTB.
0
t2
After tri-stating the HD[0:7] lines, the Host
then
asserts
nALF
to
inform
the
PPC34C60 that a data cycle is taking
place.
0
t3
The PPC34C60 will respond by placing
data on HD[0:7].
125
[3 SCLK]
1,084
[13 BCLK]
ns
t4
Then the PPC34C60 will assert the BSY
line to inform the Host that it has placed a
valid byte of data on the parallel port data
lines HD[0:7].
125
[3 SCLK]
167
[4 SCLK]
ns
t5
Next, the Host latches the data on HD[0:7]
and deasserts nALF to inform the
PPC34C60 that the cycle is complete.
42
[SCLK]
ns
t6
In response, the PPC34C60 tri-states the
parallel port data lines HD[0:7].
209
[5 SCLK]
ns
t7
After tri-stating HD[0:7] the PPC34C60
deassert BSY to indicate that it is now
ready for the next EPP transfer.
42
[SCLK]
ns
t8
As soon as the PPC34C60 deasserts BSY
the Host may initiate another EPP transfer.
This time represents the time between the
PPC34C60 deasserting BSY to the Host
starting a new transfer cycle.
0
ns
t1
t3
t6
t1
t8
t2
t5
t4
t7
VALID DATA
HD[0:7]
nSTB H
nALF H
nSEL H
nINIT H
BSY P
nACK P
PE P
SLCT P
nERR P
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