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參數(shù)資料
| 型號： | 34C60 |
| 廠商： | SMSC Corporation |
| 英文描述： | PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE |
| 中文描述： | 并行接口芯片外設(shè)端 |
| 文件頁數(shù)： | 46/58頁 |
| 文件大?。?/td> | 350K |
| 代理商： | 34C60 |
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SMSC DS – PPC34C60
Page 50
Rev. 06/01/2001
ADVANCED INFORMATION
PARAMETER
MIN
TYP
MAX
UNITS
t8
At the completion of the ECP reverse transfer cycle the
PPC34C60 either places another valid data byte on the data
lines or if it has no more data to send goes into the idle state
driving undefined data onto the parallel port bus lines. As long
as the port is in the reverse transfer mode, the PPC34C60 will
always return data when a byte is requested. Once HOST
MAX BLOCK byte-count has been reached, the PPC34C60
will present "pad" bytes to the host. The Host will discard any
extra bytes received. The extra "pad" bytes are useful to
provide alignment to wider buses.
125
[3 SCLK]
167
[4 SCLK]
ns
t9
The Host requests that the parallel port be placed back into
the forward direction by deasserting nINIT, and in response to
this the PPC34C60 will terminate any ongoing data transfer
and place the data bus HD[0:7] in a high impedance state and
deassert the BSY line.
125
[3 SCLK]
167
[4 SCLK]
ns
t10 After releasing the bus, the PPC34C60 acknowledges that it
has relinquished the bus by asserting the PE signal.
0
125
[3 SCLK]
ns
t11 After the PPC34C60 has indicated that it has relinquished the
bus, the Host may drive the data bus.
0
500
ns
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