- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄156423 > 34C60 (SMSC Corporation) PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE PDF資料下載
參數(shù)資料
| 型號： | 34C60 |
| 廠商： | SMSC Corporation |
| 英文描述： | PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE |
| 中文描述： | 并行接口芯片外設(shè)端 |
| 文件頁數(shù)： | 19/58頁 |
| 文件大?。?/td> | 350K |
| 代理商： | 34C60 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
SMSC DS – PPC34C60
Page 26
Rev. 06/01/2001
ADVANCED INFORMATION
CONFIGURATION REGISTER - 1100 (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
MAXCNT
SFIFO
rsvrd
RAMSZ1
RAMSZ0
CKSEL1
CKSEL0
The bits in this register define the configuration of the system.
Bit 7:RST
Setting this bit resets the storage elements in the chip.
Bit 6:MAXCNT
When this bit is set, the Max Block Count Registers are used to limit the bus and DRAM accesses.
Bit 5:SFIFO
This bit selects the operating mode of the Read FIFO. Setting this bit causes the internal Read FIFO to operate as a single-
word read-ahead. If this bit is clear, the Read FIFO will operate as a two-word read-ahead.
Bit 4:rsvrd
This bit is reserved and should be written as zeros.
Bits[3:2]:RAMSZ[1:0]
RAMSZ1
RAMSZ0
DRAM BUS WIDTH
0
Selects DRAM data width of 4 bits.
0
1
Selects DRAM data width of 8 bits.
1
X
Selects DRAM data width of 16 bits.
Bits[1:0]:CKSEL[1:0]
CKSEL1
CKSEL0
BUS CYCLE (BUSCLK)
0
Bus Cycle (BUSCLK) = System Clock / 2
0
1
Bus Cycle (BUSCLK) = System Clock / 3
1
0
Bus Cycle (BUSCLK) = System Clock / 5
1
Bus Cycle (BUSCLK) = System Clock / 6
BUSCLK clocks the Bus Interface State Machine responsible for generating Bus Access, DRAM access, and DRAM
Refresh timing. BUSCLK is also responsible for Output Strobe timing. System Clock is the SCLK input (pin 96) and is
typically 24MHz.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 34CMDP25B5M1RT | TOGGLE SWITCH, DPDT, MOMENTARY, 0.02A, 20VDC, PANEL MOUNT-THREADED |
| 34CMDP25B3V3RT | TOGGLE SWITCH, DPDT, MOMENTARY, 0.02A, 20VDC, THROUGH HOLE-STRAIGHT |
| 34CMDP43B4V2QT | TOGGLE SWITCH, DPDT, MOMENTARY, 3A, 28VDC, THROUGH HOLE-STRAIGHT |
| 34CMDP13B1M6RT | TOGGLE SWITCH, DPDT, LATCHED, 0.02A, 20VDC, THROUGH HOLE-RIGHT ANGLE |
| 34CMDP12B3M6QT | TOGGLE SWITCH, DPDT, LATCHED, 3A, 28VDC, THROUGH HOLE-RIGHT ANGLE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 34C7561 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DESIGN CENTER |
| 34C7563 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PLCC BREAKOUT ADAPTER BOARD |
| 34C7564 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PLCC 68 BREAKOUT ADAPTER BRD |
| 34C7565 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PLCC 84 BREAKOUT ADAPTER BRD |
| 34C7566 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:QFP 208 BREAKOUT ADAPTER BRD |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。