參數(shù)資料
型號： 03H4969
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, FP-100
文件頁數(shù)： 7/48頁
文件大小： 464K
代理商： 03H4969
Product Part Number: IBM22-ALDC1005S
ALDC1-5S
I B M Microelectronics
Document Number: DCALD5DSU-04
Data Compression
The Transfer Size register layout is given in
Figure 3-9 on page 3-5.
The direction of the data transfer operation
specifies whether the Original Data Interface
Transfer Count (TCO) register or the Com-
pressed Data Interface Transfer Count (TCC)
register is used to determine when all data
bytes have been received for the data transfer
operation. During compression, TCO is used.
During decompression, TCC is used. When the
appropriate transfer count register (TCO or
TCC) equals XFR, all bytes in the current data
transfer operation have been received by
ALDC1-5S.
3.1.8 Compressed Data Interface
Configuration (CCNF)
UPADDR: X'F'
Type: Read/Write
The Compressed Data Interface Configuration
(CCNF) register provides compressed data
interface configuration capability to the micro-
processor. CCNF is reset to X'00' by a hard-
ware or software reset.
The Compressed Data Interface Configuration
register layout is given in Figure 3-10
3.2 Interrupt
The hardware interrupt output for ALDC1-5S is
named -UPIRQ. When active (low), it indicates
that either a data transfer operation has com-
pleted successfully or that a data transfer oper-
ation has canceled prematurely due to an error.
The microprocessor determines which of these
conditions activated the hardware interrupt by
reading the Status (STAT) register and testing
the Any Error (STAT(1)) bit.
If the Any Error bit is set to one, then an error
occurred in the previously attempted data
transfer operation. The cause of the error can
then be determined by reading the Error Status
(ERRS) register. Error recovery procedures
may then be invoked as appropriate.
If the Any Error bit is zero, then no error
occurred in the previous data transfer operation
and therefore it was successful.
The hardware interrupt signal is set high (inac-
tive) automatically when either a hardware
reset or a software reset occurs, or when a new
data transfer operation is started.
Note: -UPIRQ is an open drain output and
requires a pull-up resistor. See section
Chapter 6 on page 6-1 for pull-up resistor
selection considerations.
Figure
3-10. Compressed Data Interface Con-
figuration Register
BIT
NAME/NOTES
7:4
Reserved
3:0
Compressed Data Interface FIFO
Threshold
These four bits specify the Com-
pressed Data Interface FIFO
Threshold value. Values from
B'0001' to B'1111' are valid.
Note: The reset value (B'0000')
of the Compressed Data Inter-
face FIFO Threshold bits will
cause improper operation of the
compressed data interface.
These bits must be set to a valid
value after every hardware or
software reset.
Figure
3-9. Transfer Size Register
BIT
NAME/NOTES
15:8
Transfer Size (High)
Accessed through address X'A'
on the microprocessor interface.
7:0
Transfer Size (Low)
Accessed through address X'B'
on the microprocessor interface.
Note: XFR is a sixteen bit register. This
means that the maximum data block size is
X'FFFF' (or 65,535) bytes. Therefore, the
application or system designer must ensure
that data is partitioned into data blocks
smaller than 64 kilobytes, and that each
data block is compressed and decom-
pressed separately.
See section 3.4 on page 3-6 for a dis-
cussion of data expansion.
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
3-5
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