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參數(shù)資料
| 型號： | 03H4969 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, FP-100 |
| 文件頁數(shù)： | 5/48頁 |
| 文件大?。?/td> | 464K |
| 代理商： | 03H4969 |
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Product Part Number: IBM22-ALDC1005S
ALDC1-5S
I B M Microelectronics
Document Number: DCALD5DSU-04
Data Compression
3.1.4 Compressed Data Interface
Transfer Count (TCC)
UPADDR: X'4' and X'5'
Type: Read
The Compressed Data Interface Transfer Count
(TCC) register provides the number of bytes
transferred on the compressed data interface
for a current data transfer operation. TCC is a
two byte register with the most significant byte
contained in Compressed Data Interface
Transfer Count High (TCCH) and the least sig-
nificant byte contained in Compressed Data
Interface Transfer Count Low (TCCL). TCC is
reset to X'0000' by a hardware or software
reset. Also, TCC is reset to X'0000' when a
data transfer operation is initialized.
The Compressed Data Interface Transfer Count
register layout is given in Figure 3-5.
During a decompression operation, TCC is
incremented as each compressed data byte is
received by the compressed data interface.
When TCC equals XFR during decompression,
all bytes in the decompression operation have
been received by ALDC1-5S.
During a compression operation, TCC is incre-
mented as each compressed data byte is sent
by the compressed data interface.
3.1.5 Error Status (ERRS)
UPADDR: X'6'
Type: Read
The Error Status (ERRS) register provides error
status bits to the microprocessor. ERRS is
reset to X'00' by a hardware or software reset.
The Error Status register layout is given in
Figure 3-6.
Figure
3-4 (Page 2 of 2). Original Data Inter-
face Transfer Count Register
BIT
NAME/NOTES
7:0
Original Data Interface Transfer
Count (Low)
Accessed through address X'3'
on the microprocessor interface.
Notes:
1. Because of the time needed to complete
any outstanding compression oper-
ations on the final bytes received during
compression, TCO cannot be used to
determine when the compression oper-
ation is complete. The Done (STAT(0))
bit is used for this purpose.
2. TCO is a sixteen bit register.
Attempting to transfer 64 kilobytes or
more data will result in a TCO register
overflow. Therefore, the application or
system designer must ensure that data
is partitioned into data blocks smaller
than 64 kilobytes, and that each data
block is compressed and decompressed
separately.
See section 3.4 on page 3-6 for a dis-
cussion of data expansion.
Figure
3-5. Compressed Data Interface
Transfer Count Register
BIT
NAME/NOTES
15:8
Compressed Data Interface
Transfer Count (High)
Accessed through address X'4'
on the microprocessor interface.
7:0
Compressed Data Interface
Transfer Count (Low)
Accessed through address X'5'
on the microprocessor interface.
Notes:
1. Because of the time needed to complete
any outstanding decompression oper-
ations on the final bytes received during
decompression, TCC cannot be used to
determine when the decompression
operation is complete. The Done
(STAT(0)) bit is used for this purpose.
2. TCC is a sixteen bit register.
Attempting to transfer 64 kilobytes or
more data will result in a TCC register
overflow. Therefore, the application or
system designer must ensure that data
is partitioned into data blocks smaller
than 64 kilobytes, and that each data
block is compressed and decompressed
separately.
See section 3.4 on page 3-6 for a dis-
cussion of data expansion.
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
3-3
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