參數(shù)資料
型號(hào)： 03H4969
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, FP-100
文件頁數(shù)： 47/48頁
文件大小： 464K
代理商： 03H4969
Product Part Number: IBM22-ALDC1005S
ALDC1-5S
I B M Microelectronics
Document Number: DCALD5DSU-04
Data Compression
2.1.5 ALDC Encoder
The ALDC encoder accepts data bytes from the
original data interface and provides com-
pressed data bytes to the compressed data
interface. The ALDC implementation of the
adaptive Lempel-Ziv lossless compression
algorithm accomplishes this function.
The ALDC encoder contains a 512-byte content
addressable memory (CAM). The CAM is the
history buffer during compression operations.
The ALDC encoder concatenates an end
marker control code to the end of the com-
pressed data. It also pads any remaining bits
with zeros to align evenly on a byte boundary.
2.1.6 ALDC Decoder
The ALDC decoder accepts compressed data
bytes from the compressed data interface and
provides the reconstructed data bytes to the
original data interface. The ALDC implementa-
tion of the adaptive Lempel-Ziv lossless com-
pression algorithm accomplishes this function.
The ALDC decoder contains a 512-byte random
access memory (RAM). The RAM is the history
buffer during decompression operations.
The ALDC decoder expects to find an end
marker control code in the final data received
from the compressed data interface. If it does
not detect the end marker control code, then it
asserts an ALDC decoder end error. If it
detects the end marker control code, then it
strips the end marker control code from the
decompressed data stream.
2.2 Data Transfer Operations
The ALDC1-5S has two data transfer operations.
These are compression and decompression.
The data transfer operations allow data to pass
between the original data interface and the
compressed data interface. It is important to
note that data passes
through ALDC1-5S.
ALDC1-5S carries out the appropriate oper-
ations on the data as it flows from source (ie.
external direct memory access device) to desti-
nation (external direct memory access con-
troller) and, later, when it flows back again.
The Transfer Size (XFR) register specifies the
number of bytes to transfer during the data
transfer operation. This number is sometimes
called the
frame size. The microprocessor must
load the XFR register before a data transfer
operation can begin.
The Compressed Data Interface Configuration
(CCNF) register specifies the Compressed Data
Interface FIFO Threshold value. This value
tunes compressed data interface performance
to meet application or system requirements.
The microprocessor typically loads the CCNF
register after hardware and software resets.
For more information, see 4.3.1 on page 4-9.
The Command (CMND) register specifies which
data transfer (or other) operation to perform.
When the microprocessor writes a Start Com-
pression or Start Decompression opcode into
the CMND register, then the data transfer oper-
ation begins. The transfer proceeds until it is
complete, a reset occurs, or an error occurs. If
an error occurs, ALDC1-5S sets the appropriate
error status bits, asserts the -UPIRQ output, and
cancels the transfer operation. Depending on
the type of error, the microprocessor may reset
ALDC1-5S, attempt to retry the entire transfer,
and/or report the failure. When data transfer is
successful, ALDC1-5S sets the Done (STAT(0))
bit to one and asserts the -UPIRQ output.
After a data transfer operation has ended, the
microprocessor prepares ALDC1-5S for the next
operation. The -UPIRQ returns high (inactive)
automatically when a new data transfer opera-
tion starts or when a reset occurs.
2.2.1 Compression
The original data interface receives data from
the external direct memory access device and
sends it to the ALDC encoder. The ALDC
encoder compresses the data and sends it to
the compressed data interface. The com-
pressed data interface sends the compressed
data to the external direct memory access con-
troller.
The following sequence occurs:
1. ALDC1-5S clears the history buffer, resets
the transfer count registers (TCO and TCC)
to X'0000', resets the Error Status (ERRS)
register to X'00', and sets the Status
(STAT) register to X'80' (ie. Busy).
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
2-2
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