參數(shù)資料
型號： μPD78F9177Y
廠商： NEC Corp.
英文描述： 8 Bit Single Chip Microcontrollers(8 位單片微控制器)
中文描述： 8位單片機微控制器（8位單片微控制器）
文件頁數(shù)： 86/150頁
文件大小： 653K
代理商： ΜPD78F9177Y
Preliminary Product Information
84
μ
PD78F9177Y
Figure 6-39. Format of SMB Status Register 0 (2/3)
COI0
0
1
Clear conditions (COI0 = 0)
Cleared upon detection of start condition
Cleared upon detection of stop condition
Cleared when LREL0 = 1
Cleared when SMBE0 changes from 1 to 0
Cleared by RESET input
Set conditions (COI0 = 1)
Set when received address matches local address
(SVA0) (set at rising edge of 8th clock)
Matching address detection
Address does not match.
Address matches.
ACKD0
0
1
Clear conditions (ACKD0 = 0)
Cleared upon detection of stop condition
Cleared at rising edge of 1st clock of following byte
Cleared when LREL0 = 1
Cleared when SMBE0 changes from 1 to 0
Cleared by RESET input
Acknowledge output
Does not detect acknowledge.
Detects acknowledge.
TRC0
0
1
Clear conditions (TRC0 = 0)
Cleared upon detection of stop condition
Cleared when LREL0 = 1
Cleared SMBE0 changes from 1 to 0
Cleared when WREL0 = 1
Cleared when ALD0 changes from 0 to 1
Cleared by RESET input
In case of master:
When "1" is output to 1st byte LSB
(transmission direction specification bit)
In case of slave:
Upon detection of start condition
In case of non-participation in communication
Receive/send status detection
Receive status (when not in send status). Sets SDA0 line to high impedance.
Send status. Sets so that SO latch value can be output to SDA0 line (valid from falling edge of
9th clock of 1st byte).
Set conditions (TRC0 = 1)
In case of master:
Upon generation of start condition
In case of slave:
When "1" is input to 1st byte LSB (transmission
direction specification bit)
Set conditions (ACKD0 = 1)
Set when SDA0 line is low level at rising edge of
9th clock of SCL0
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