參數(shù)資料
型號： μPD78F9177Y
廠商： NEC Corp.
英文描述： 8 Bit Single Chip Microcontrollers(8 位單片微控制器)
中文描述： 8位單片機微控制器（8位單片微控制器）
文件頁數(shù)： 131/150頁
文件大?。?/td> 653K
代理商： ΜPD78F9177Y
Preliminary Product Information
129
μ
PD78F9177Y
SERIAL INTERFACE (T
A
=
40
°
C to +85
°
C, V
DD
= 1.8 to 5.5 V)
(a) Serial interface 20
(i) Three-wire serial I/O mode (SCK...Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY1
V
DD
= 2.7 to 5.5 V
800
ns
3,200
ns
t
KH1
, t
KL1
V
DD
= 2.7 to 5.5 V
t
KCY1
/2
50
ns
t
KCY1
/2
150
ns
t
SIK1
V
DD
= 2.7 to 5.5 V
150
ns
500
ns
t
KSI1
V
DD
= 2.7 to 5.5 V
400
ns
600
ns
t
KSO1
V
DD
= 2.7 to 5.5 V
0
250
ns
0
1,000
ns
Note
R and C are the resistance and capacitance of the SO output line, respectively.
(ii) Three-wire serial I/O mode (SCK...External clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY2
V
DD
= 2.7 to 5.5 V
800
ns
3,200
ns
t
KH2
, t
KL2
V
DD
= 2.7 to 5.5 V
400
ns
1,600
ns
t
SIK2
V
DD
= 2.7 to 5.5 V
100
ns
150
ns
t
KSI2
V
DD
= 2.7 to 5.5 V
400
ns
600
ns
t
KSO2
V
DD
= 2.7 to 5.5 V
0
300
ns
0
1,000
ns
Note
R and C are the resistance and capacitance of the SO output line, respectively.
(iii) UART mode (internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Transfer rate
V
DD
= 2.7 to 5.5 V
78,125
bps
19,531
bps
SCK high/low level
width
SI setup time
(for SCK
↑
)
SI hold time
(for SCK
↑
)
Delay from SCK
↓
to SO output
SCK high/low level
width
SI setup time
(for SCK
↑
)
SI hold time
(for SCK
↑
)
Delay from SCK
↓
to SO output
R = 1 k
,
C = 100 pF
Note
R = 1 k
,
C = 100 pF
Note
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