參數(shù)資料
型號： μPD78F9177Y
廠商： NEC Corp.
英文描述： 8 Bit Single Chip Microcontrollers(8 位單片微控制器)
中文描述： 8位單片機微控制器（8位單片微控制器）
文件頁數(shù)： 61/150頁
文件大小： 653K
代理商： ΜPD78F9177Y
Preliminary Product Information
59
μ
PD78F9177Y
Figure 6-28. Block Diagram of A/D Converter
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison
voltage), received from the serial resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to the A/D conversion result register.
(2) A/D conversion result register 0 (ADCR0)
The ADCR holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received
from the successive approximation register is loaded into the ADCR0.
The value of ADCR0 is read using a 16-bit memory manipulation instruction.
A RESET input makes ADCR0 undefined.
Caution
When the
μ
PD78F9177Y is used as flash memory for the
μ
PD789166Y or
μ
PD789167Y,
8-bit access is allowed. However, only those object files generated by an assembler used
with the
μ
PD789166Y or
μ
PD789167Y are supported for this access.
(3) Sample-and-hold circuit
The sample-and-hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the serial resistor string.
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
Sample-and-hold circuit
Voltage comparator
Control
circuit
Successive
approximation
register (SAR)
3
A/D conversion result
register 0 (ADCR0)
T
S
AV
SS
INTAD0
A/D conveter mode register 0
(ADM0)
A/D input selection register 0
(ADS0)
Internal bus
AV
SS
ADCS0
0
FR02 FR01 FR00
0
0
0
ADS02ADS01ADS00
AV
REF
AV
DD
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