參數(shù)資料
型號: μPD45D128164
廠商: NEC Corp.
英文描述: 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM)
中文描述: 128 M位同步雙數(shù)據(jù)速率(128同步動態(tài)RAM的內(nèi)存)
文件頁數(shù): 35/80頁
文件大?。?/td> 637K
代理商: ΜPD45D128164
35
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
12.2 Precharge Termination in Read Cycle
During a burst read cycle without auto precharge, the burst read operation is terminated by a precharge command of
the same banks. When the precharge command is issued at the rising edge of the clock (CLK), the burst read
operation is terminated and the data bus goes to high impedance after the /CAS latency from the precharge
command. The precharge command can be issued after t
RAS (MIN.)
is satisfied.
CLK
Burst length = Full page
Q1
Q2
Q3
READ
DQ
Command
Q4
Q1
Q2
DQ
Command
Q3
Q4
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
READ
(When t
RAS
is satisfied)
PRE
PRE
Hi-Z
Hi-Z
T0
T2
T1
T3
T4
T5
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μPD45D128442 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM)
μPD45D128842 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM)
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