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參數(shù)資料
| 型號： | μPD45D128164 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM) |
| 中文描述： | 128 M位同步雙數(shù)據(jù)速率（128同步動態(tài)RAM的內(nèi)存） |
| 文件頁數(shù)： | 28/80頁 |
| 文件大?。?/td> | 637K |
| 代理商： | ΜPD45D128164 |
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28
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
10. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the read or
write command (read with auto precharge command or write with auto precharge command), auto precharge is
selected and begin automatically.
The t
RAS
must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.
In read cycle, once auto precharge has started, an activate command to the bank can be issued after t
RP
has been
satisfied.
In write cycle, the t
DAL
must be satisfied to issue the next activate command to the bank being precharged.
10.1 Read with Auto Precharge
When a read with auto precharge command is issued, the auto precharge begins (Burst length / 2) clocks later from
a read with auto precharge command.
CLK
Burst length = 4
T5
Q1
Q2
Q3
READA
DQ
Command
Q4
Q1
Q2
DQ
Command
Q3
Q4
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
READA
Burst length / 2 cycle
(When t
RAS
is satisfied)
ACT
ACT
Hi-Z
Hi-Z
t
RP
Auto precharge starts
Auto precharge starts
T0
T2
T1
T3
T4
Remark
READA means Read with Auto Precharge command
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| μPD45D128442 | 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM) |
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